Claas Cornelius

According to our database1, Claas Cornelius authored at least 16 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Effiziente Simulation von Gateoxiddefekten auf Gatterebene mit Transistorlevel-Genauigkeit.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits.
J. Low Power Electron., 2011

Reliability enhancement via Sleep Transistors.
Proceedings of the 12th Latin American Test Workshop, 2011

Functional enhancements of TMR for power efficient and error resilient ASIC designs.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Monitoring and Control of Temperature in Networks-on-Chip.
Proceedings of the Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2010

Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Modeling temperature distribution in Networks-on-Chip using RC-circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Differences and Commonalities of Service-Oriented Device Architectures, Wireless Sensor Networks and Networks-on-Chip.
Proceedings of the 23rd International Conference on Advanced Information Networking and Applications, 2009

2008
Encountering gate oxide breakdown with shadow transistors to increase reliability.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

2007
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Mapping a Pipelined Data Path onto a Network-on-Chip.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2006
Mixed Gates: Leakage Reduction techniques applied to Switches for Networks-on-Chip.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Reduzierung des Leckstromverbrauchs mit gemischten Gattern in Deep Submicron Technologien.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

2005
Verlustleistungsreduzierung bei dynamischen TSPC-Schaltungstechniken.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005


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