Ciaran J. Brennan

According to our database, Ciaran J. Brennan authored at least 4 papers between 2004 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2007

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.

Ciaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier

Microelectron. Reliab., 2007

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.

Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier

Microelectron. Reliab., 2007

2004

Power network analysis for ESD robustness in a 90nm ASIC design system.

Ciaran J. Brennan, Joseph N. Kozhaya, Robert A. Proctor

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

BIST controlled variable sense amp timing for 90nm embedded SRAM.

Ciaran J. Brennan, Steven Eustis, John Goss, A. Humphrey, Michael Ouellette, Jeremy Rowland, Michael Fragano

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004