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We stand with Ukraine

Chunseok Jeong

Orcid: 0009-0004-1666-7878

According to our database¹, Chunseok Jeong authored at least 14 papers between 2016 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2024

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology.

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Myeong-Jae Park

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IEEE Access, 2024

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.

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[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System.

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[DOI]

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.

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Kyeong Pil Kang

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Kornijcuk Vladimir

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IEEE J. Solid State Circuits, 2023

Memory-Centric Computing with SK Hynix's Domain-Specific Memory.

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Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.

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Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Holistic approaches to memory solutions for the Autonomous Driving Era.

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Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

System Architecture and Software Stack for GDDR6-AiM.

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Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

2020

Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning.

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Mithuna Thottethodi

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T. N. Vijaykumar

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.

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[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller.

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Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control.

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Myeong-Jae Park

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Seung Geun Baek

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Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.

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Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

High bandwidth memory(HBM) with TSV technique.

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Proceedings of the International SoC Design Conference, 2016

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