Chung-Yu Wu
Orcid: 0000-0002-9236-0809
According to our database1,
Chung-Yu Wu
authored at least 147 papers
between 1985 and 2024.
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Bibliography
2024
Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications.
IEEE Trans. Biomed. Circuits Syst., June, 2024
2023
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
2022
Design and Ex Vivo Experimental Validations of the CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip With Auto-Adaptive Pixels for a Wide Image Illuminance Range.
IEEE Trans. Biomed. Eng., 2022
Design of CMOS Analog Front-End Electroencephalography (EEG) Amplifier with ±1-V Common-mode and ±10-mV Differential-mode Artifact Removal.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits, 2021
2020
CMOS High-Efficiency Wireless Battery Charging System With Global Power Control Through Backward Data Telemetry for Implantable Medical Devices.
IEEE Trans. Circuits Syst., 2020
CMOS 256-Pixel/480-Pixel Photovoltaic-Powered Subretinal Prosthetic Chips With Wide Image Dynamic Range and Bi/Four-Directional Sharing Electrodes and Their Ex Vivo Experimental Validations With Mice.
IEEE Trans. Circuits Syst., 2020
Improved Charge Pump Design and Ex Vivo Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip.
IEEE Trans. Biomed. Eng., 2020
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Biomed. Eng., 2019
A CMOS 256-Pixel Self-Photovoltaics-Powered Subretinal Prosthetic Chip with Wide Image Dynamic Range and Shared Electrodes and Its In Vitro Experimental Results on Rd1 Mice.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A 2.36μW/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
The Design of CMOS Electrode-Tissue Impedance Measurement Circuit Using Differential Current Switch with CMFB Bias for Implantable Neuro-Modulation SoCs.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
2018
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.
IEEE Trans. Biomed. Circuits Syst., 2018
Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2018
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2018
The Design of CMOS 13.56-MHz High Efficiency 1×/3× 1.99V/6.29V Active Rectifier for Implantable Neuromodulation Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018
2017
A 16-channel CMOS chopper-stabilized analog front-end acquisition circuits for ECoG detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A gradient vector flow snake based multi-level morphological active contour algorithm.
Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017
Design considerations and clinical applications of closed-loop neural disorder control SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
The design of 8-channel CMOS area-efficient low-power current-mode analog front-end amplifier for EEG signal recording.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Biomed. Eng., 2015
An 8-channel power-efficient time-constant-enhanced analog front-end amplifier for neural signal acquisition.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A microfabricated coil for implantable applications of magnetic spinal cord stimulation.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
The design of CMOS self-powered 256-pixel implantable chip with on-chip photovoltaic cells and active pixel sensors for subretinal prostheses.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices.
IEEE J. Solid State Circuits, 2014
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2014
A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A CMOS Power-Efficient Low-Noise Current-Mode Front-End Amplifier for Neural Signal Recording.
IEEE Trans. Biomed. Circuits Syst., 2013
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A MedRadio-band low-energy-per-bit 4-Mbps CMOS OOK receiver for implantable medical devices.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
2012
A low-power current-mode front-end acquisition system for biopotential signal recording.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Live demonstration: The implementation of CMOS biopotential signal recording systems.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
IEICE Trans. Electron., 2011
The design of CMOS general-purpose analog front-end circuit with tunable gain and bandwidth for biopotential signal recording systems.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
2010
Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Stability Analysis of Autonomous Ratio-Memory Cellular Nonlinear Networks for Pattern Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications.
IEICE Trans. Electron., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network.
Integr., 2009
IEICE Trans. Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-μm CMOS Technology.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
An efficient Compensation Method for Improving Luminance Uniformity of Organic Light Emitting Diode Panels.
Proceedings of the 2007 International Conference on Scientific Computing, 2007
2006
A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A new CMOS pixel structure for low-dark-current and large-array-size still imager applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator.
IEEE J. Solid State Circuits, 2004
A low-power implantable Pseudo-BJT-based silicon retina with solar cells for artificial retinal prostheses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
A learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for associative memory applications.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
A low power design on diffusive interconnection large-neighborhood cellular nonlinear network for giga-scale system application.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
2003
An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
Improvement of pattern learning and recognition capability in ratio-memory cellular neural networks with non-discrete-type Hebbian learning algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
IEEE J. Solid State Circuits, 2001
The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A new light-activated CMOS retinal-pulse generation circuit without external power supply for artificial retinal prostheses.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
The design of CMOS real-time motion-direction detection chip with BJT-based silicon-retina sensors and correlation-based motion detection algorithm.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
The new CMOS 2 V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A compact CMOS 2 V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9 GHz RF transmitter applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications.
IEEE J. Solid State Circuits, 1999
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
The design of CMOS cellular neural network (CNN) using the neuron-bipolar junction transistor (νBJT).
Proceedings of the International Joint Conference Neural Networks, 1999
A new compact programmable νBJT cellular neural network structure with adjustable neighborhood layers for image processing.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
The design of 2 V 2.4 GHz CMOS low-noise low-power bandpass amplifier with parallel spiral inductors.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
A 3 V 1.9 GHz CMOS low-distortion direct-conversion quadrature modulator with a RF amplifier.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications.
IEEE J. Solid State Circuits, 1998
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA.
IEEE J. Solid State Circuits, 1998
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer.
IEEE J. Solid State Circuits, 1998
The neuron-bipolar junction transistor (v-BJT)-a new device structure for VLSI neural network implementation.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
The design of 2 V 1 GHz CMOS low-noise bandpass amplifier with good temperature stability and low power dissipation.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
IEEE Trans. Circuits Syst. Video Technol., 1997
IEEE J. Solid State Circuits, 1997
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs.
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
IEEE Trans. Neural Networks, 1996
IEEE Trans. Neural Networks, 1996
The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits.
IEEE J. Solid State Circuits, 1996
Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers.
IEEE J. Solid State Circuits, 1996
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter.
IEEE J. Solid State Circuits, 1996
Bipolar bootstrapped multi-emitter BiCMOS (B<sup>2</sup>M-BiCMOS) logic for low-voltage applications.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
A new design technique of CMOS continuous-time VHF current-mode bandpass ladder filters using VHF bandpass biquads.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
1995
IEEE J. Solid State Circuits, August, 1995
A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques.
IEEE J. Solid State Circuits, May, 1995
IEEE J. Solid State Circuits, January, 1995
Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques.
IEEE J. Solid State Circuits, January, 1995
CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition.
J. VLSI Signal Process., 1995
A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock Boosters.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A 3-V 1-GHz Low-Noise Bandpass Amplifier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Analog CMOS current-mode implementation of the feedforward neural network with on-chip learning and storage.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
1994
A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources.
IEEE J. Solid State Circuits, November, 1994
IEEE J. Solid State Circuits, September, 1994
The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement Circuit.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
VHF/UHF High-Q Bandpass Tunable Filters Design Using CMOS Inverter-Based Transresistnace Amplifiers.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion Cycle.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
VHF Bandpass Filter Design Using CMOS Transresistance Amplifiers.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A Ratio-independent and Gain-insensitive Algorithmic Analog-to-digital Converter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Chopper-stabilized Sigma-delta Modulator.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1990
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985