Chung-Yang Huang
According to our database1,
Chung-Yang Huang
authored at least 43 papers
between 1998 and 2022.
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Bibliography
2022
2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2017
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017
2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2014
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
A robust constraint solving framework for multiple constraint sets in constrained random verification.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012
A robust general constrained random pattern generator for constraints with variable ordering.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Property-specific sequential invariant extraction for SAT-based unbounded model checking.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Computers, 2010
A robust functional ECO engine by SAT proof minimization and interpolation techniques.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
A false-path aware formal static timing analyzer considering simultaneous input transitions.
Proceedings of the 46th Design Automation Conference, 2009
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification.
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Scalable exploration of functional dependency by interpolation and incremental SAT solving.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2001
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
2000
IEEE Trans. Computers, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.
Proceedings of the 37th Conference on Design Automation, 2000
1998
Proceedings of the 1998 International Symposium on Physical Design, 1998