Chung-Wen Albert Tsao

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

UST/DME: a clock tree router for general skew constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Power Supply Noise Suppression via Clock Skew Scheduling.

[BibT_eX]

[DOI]

Wai-Ching Douglas Lam

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

1998

Bounded-skew clock and Steiner routing.

[BibT_eX]

[DOI]

Jason Cong

ACM Trans. Design Autom. Electr. Syst., 1998

1997

Practical Bounded-Skew Clock Routing.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1997

More Practical Bounded-Skew Clock Routing.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Planar-DME: a single-layer zero-skew clock tree router.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods.

[BibT_eX]

[DOI]

T. C. Hu

INFORMS J. Comput., 1995

Bounded-skew clock and Steiner routing under Elmore delay.

[BibT_eX]

[DOI]

Jason Cong

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

On the Bounded-Skew Clock and Steiner Routing Problems.

[BibT_eX]

[DOI]

Dennis J.-H. Huang

Proceedings of the 32st Conference on Design Automation, 1995

1994

Low-cost single-layer clock trees with exact zero Elmore delay skew.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

1993

Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD.

[BibT_eX]

[DOI]

Kenneth D. Boese