Chung-Ting Lu

According to our database, Chung-Ting Lu authored at least 3 papers between 2010 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.

Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2016

A 0.034mm², 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2010

A Low-Power Quadrature VCO and Its Application to a 0.6-V 2.4-GHz PLL.

Chung-Ting Lu, Hsieh-Hung Hsieh, Liang-Hung Lu

IEEE Trans. Circuits Syst. I Regul. Pap., 2010