Chung-Shiang Wu
Orcid: 0000-0002-4708-8148
According to our database1,
Chung-Shiang Wu
authored at least 9 papers
between 2014 and 2019.
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Bibliography
2019
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper).
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting.
IEEE J. Solid State Circuits, 2016
2015
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
Proceedings of the VLSI Design, Automation and Test, 2015
20.10 A 50nW-to-10mW output power tri-mode digital buck converter with self-tracking zero current detection for photovoltaic energy harvesting.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014