Chung-Ping Chung

J. Inf. Sci. Eng., 2015

2014

Extended Instruction Exploration for Multiple-Issue Architectures.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering.

[BibT_eX]

[DOI]

Tsung-Hsi Weng

Future Gener. Comput. Syst., 2014

2011

Load and storage balanced posting file partitioning for parallel information retrieval.

[BibT_eX]

[DOI]

J. Syst. Softw., 2011

Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration.

[BibT_eX]

[DOI]

I-Wei Wu

J. Inf. Sci. Eng., 2011

Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity.

[BibT_eX]

[DOI]

Walter Yuan-Hwa Li

Chin-Ling Huang

Proceedings of the International Conference on Parallel Processing, 2011

Set Utilization Based Dynamic Shared Cache Partitioning.

[BibT_eX]

[DOI]

Peter Deayton

Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering.

[BibT_eX]

[DOI]

Tsung-Hsi Weng

Yi-Ting Wang

Proceedings of the Algorithms and Architectures for Parallel Processing, 2011

2010

Reconfigurable custom functional unit generation and exploitation in multiple-issue processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2009

Smaller Split L-1 Data Caches for Multi-core Processing Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Pervasive Systems, 2009

Methods for Precise False-Overlap Detection in Tile-Based Rendering.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

A Hierarchical Primitive Lists Structure for Tile-Based Rendering.

[BibT_eX]

[DOI]

Chih-Chieh Hsiao

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method.

[BibT_eX]

[DOI]

Tung-Lin Lu

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads.

[BibT_eX]

[DOI]

Hong-Wei Chen

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008

Filtering of Unnecessary Branch Predictor Lookups for Low-power Processor Architecture.

[BibT_eX]

[DOI]

Wei-Hau Chiao

J. Inf. Sci. Eng., 2008

iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability.

[BibT_eX]

[DOI]

Li-Ming Wang

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Instruction Set Extension Exploration in Multiple-Issue Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Mechanism for return stack and branch history corrections under misprediction in deep pipeline design.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

Early load: Hiding load latency in deep pipeline processor.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007

Instruction Set Extension Generation with Considering Physical Constraints.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing.

[BibT_eX]

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A Run-Time Reconfigurable Fabric for 3D Texture Filtering.

[BibT_eX]

[DOI]

Wei-Ting Wang

Yi-Chi Chen

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems.

[BibT_eX]

[DOI]

Cher-Sheng Cheng

Inf. Process. Manag., 2006

Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems.

[BibT_eX]

[DOI]

Cher-Sheng Cheng

Inf. Process. Manag., 2006

Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability.

[BibT_eX]

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer.

[BibT_eX]

Bin-Hua Tein

I-Wei Wu

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005

Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving.

[BibT_eX]

[DOI]

Ching-Wen Chen

J. Supercomput., 2005

A statistics-based approach to incrementally update inverted files.

[BibT_eX]

[DOI]

Wann-Yun Shieh

Inf. Process. Manag., 2005

Low-Power Branch Prediction.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

Low-Power Data Address Bus Encoding Method.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

2004

A software/hardware cooperated stack operations folding model for Java processors.

[BibT_eX]

[DOI]

J. Syst. Softw., 2004

Code compression by register operand dependency.

[BibT_eX]

[DOI]

Kelvin Lin

J. Syst. Softw., 2004

Branch-and-bound task allocation with task clustering-based pruning.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2004

A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems.

[BibT_eX]

[DOI]

Cher-Sheng Cheng

Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

2003

Compressing MIPS code by multiple operand dependencies.

[BibT_eX]

[DOI]

Kelvin Lin

ACM Trans. Embed. Comput. Syst., 2003

Variable-size data item placement for load and storage balancing.

[BibT_eX]

[DOI]

J. Syst. Softw., 2003

3-Disjoint gamma interconnection networks.

[BibT_eX]

[DOI]

Ching-Wen Chen

J. Syst. Softw., 2003

An Inverted File Cache for Fast Information Retrieval.

[BibT_eX]

[DOI]

Wann-Yun Shieh

J. Inf. Sci. Eng., 2003

Inverted file compression through document identifier reassignment.

[BibT_eX]

[DOI]

Inf. Process. Manag., 2003

A Tree-Based inverted File for Fast Ranked-Document Retrieval.

[BibT_eX]

Wann-Yun Shieh

Proceedings of the International Conference on Information and Knowledge Engineering. IKE'03, June 23, 2003

2002

Design of an optimal folding mechanism for Java processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2002

Posting file partitioning and parallel information retrieval.

[BibT_eX]

[DOI]

J. Syst. Softw., 2002

An analytical POC stack operations folding for continuous and discontinuous Java bytecodes.

[BibT_eX]

[DOI]

Lee-Ren Ton

Lung-Chung Chang

J. Syst. Archit., 2002

Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.

[BibT_eX]

[DOI]

Jih-Ching Chiu

Michael Jin-Yi Wang

J. Inf. Sci. Eng., 2002

2001

A dominance relation enhanced branch-and-bound task allocation.

[BibT_eX]

[DOI]

J. Syst. Softw., 2001

Fault-tolerant gamma interconnection network without backtracking.

[BibT_eX]

[DOI]

Ching-Wen Chen

J. Syst. Softw., 2001

2000

Applying stack simulation for branch target buffers.

[BibT_eX]

[DOI]

R.-Ming Shiu

J. Syst. Softw., 2000

Design of Instruction Stream Buffer with Trace Support for X86 Processors.

[BibT_eX]

[DOI]

Jih-Ching Chiu

I-Huan Huang

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note).

[BibT_eX]

[DOI]

Lee-Ren Ton

Lung-Chung Chang

Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999

Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System.

[BibT_eX]

Ruey-Liang Ma

J. Inf. Sci. Eng., 1999

1997

Instruction Folding in Java Processor.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

Instruction Cache Prefetching with Extended BTB.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

1996

A Fault-Tolerant Multistage Combining Network.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1996

[BibT_eX]

[DOI]

Chang-Chung Liu

R.-Ming Shiu

Proceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), 1996

1995

An Optimal Instruction Scheduler for Superscalar Processor.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1995

Memory System Design in Superscalar Processing.

[BibT_eX]

[DOI]

Int. J. High Speed Comput., 1995

An Approximate Agreement Algorithm for Wraparound Meshes.

[BibT_eX]

[DOI]

Ren-Lianq Cheng

Int. J. High Speed Comput., 1995

Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog.

[BibT_eX]

[DOI]

Ruey-Liang Ma

Comput. J., 1995

1994

Effects and Handling of Instruction Class Contention in Superscalar Processing.

[BibT_eX]

[DOI]

Yuh-Horng Shiau

Int. J. High Speed Comput., 1994

Optimal multiprocessor task scheduling using dominance and equivalence relations.

[BibT_eX]

[DOI]

Comput. Oper. Res., 1994

Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog.

[BibT_eX]

[DOI]

Ruey-Liang Ma

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

Delayed Precise Invalidation - A Software Cache Coherence Scheme.

[BibT_eX]

[DOI]

Tang-Show Hwang

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993

Reaching Approximate Agreement on Hypercube.

[BibT_eX]

[DOI]

Ren-Lianq Cheng

Parallel Comput., 1993

Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm.

[BibT_eX]

[DOI]

BIT, 1993

1992

Adoptability and effectiveness of microcode compaction algorithms in superscalar processing.

[BibT_eX]

[DOI]

Yuh-Horng Shiau

Parallel Comput., 1992

A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle.

[BibT_eX]

[DOI]

Parallel Comput., 1992

Vectorization of Sorting Algorithms.

[BibT_eX]

[DOI]

Wen-Yang Lin

Int. J. High Speed Comput., 1992

Upper Bound Analysis of Scheduling Arbitrary-Delay Instructions on Typed Pipelined Processors.

[BibT_eX]

[DOI]