Chung-Kuan Cheng
Orcid: 0000-0002-9865-8390Affiliations:
- University of California, San Diego, USA
According to our database1,
Chung-Kuan Cheng
authored at least 294 papers
between 1984 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2000, "For contributions to circuit partitioning and physical layout automation.".
Timeline
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Bibliography
2024
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations.
CoRR, 2024
2023
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs.
ACM Trans. Design Autom. Electr. Syst., July, 2023
Using EEG Signals to Assess Workload during Memory Retrieval in a Real-world Scenario.
CoRR, 2023
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints.
Proceedings of the 2023 International Symposium on Physical Design, 2023
2022
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2022
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim., 2022
IEEE Embed. Syst. Lett., 2022
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation.
IEEE Des. Test, 2022
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access, 2022
Placement initialization via a projected eigenvector algorithm: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Embed. Syst. Lett., 2021
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs.
Networks, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
2018
Proceedings of the 2018 International Symposium on Physical Design, 2018
Proceedings of the 2018 International Symposium on Physical Design, 2018
Transient circuit simulation for differential algebraic systems using matrix exponential.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018
2017
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2016
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction.
Int. J. Circuit Theory Appl., 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method.
ACM Trans. Design Autom. Electr. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
CoRR, 2015
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015
Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators.
Proceedings of the 52nd Annual Design Automation Conference, 2015
An interdigitated non-contact ECG electrode for impedance compensation and signal restoration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Power grid simulation using matrix exponential method with rational Krylov subspaces.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
Globally stable, highly parallelizable fast transient circuit simulation via faber series.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the International Symposium on Physical Design, 2012
Circuit simulation via matrix exponential method for stiffness handling and parallel processing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Character design and stamp algorithms for Character Projection Electron-Beam Lithography.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
More realistic power grid verification based on hierarchical current and power constraints.
Proceedings of the 2011 International Symposium on Physical Design, 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
ACM Trans. Design Autom. Electr. Syst., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010
Worst-case noise prediction with non-zero current transition times for early power distribution system verification.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards.
IEEE Trans. Educ., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design.
IEICE Trans. Electron., 2009
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
On the bound of time-domain power supply noise based on frequency-domain target impedance.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
Design methodology of high performance on-chip global interconnect using terminated transmission-line.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
High performance on-chip differential signaling using passive compensation for global communication.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
2008
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
J. Comput. Sci. Technol., 2006
Proceedings of the 2006 International Symposium on Physical Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the Sixth IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2006), 2006
An unconditional stable general operator splitting method for transistor level transient analysis.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 2005 International Symposium on Physical Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
A multi-level transmission line network approach for multi-giga hertz clock distribution.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Handbook of Data Structures and Applications., 2004
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst., 2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Sci. China Ser. F Inf. Sci., 2004
Sci. China Ser. F Inf. Sci., 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
A multiple level network approach for clock skew minimization with process variations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Proceedings of the 2003 International Symposium on Physical Design, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
J. Comput. Sci. Technol., 2002
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
2000
An enhanced perturbing algorithm for floorplan design using the O-tree representation.
Proceedings of the 2000 International Symposium on Physical Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Block placement with symmetry constraints based on the O-tree non-slicing representation.
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation.
Proceedings of ASP-DAC 2000, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Timing optimization for multisource nets: characterization andoptimal repeater insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the 1998 International Symposium on Physical Design, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the 34st Conference on Design Automation, 1997
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
IEEE J. Solid State Circuits, 1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
Proceedings of the 33st Conference on Design Automation, 1996
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Performance-Driven Partitioning Using a Replication Graph Approach.
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
<i>Prime</i>: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
An optimal probe testing algorithm for the connectivity verification of MCM substrates.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm.
Proceedings of the 28th Design Automation Conference, 1991
1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
1988
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
1987
1984
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984