Chung-Ju Wu

According to our database1, Chung-Ju Wu authored at least 9 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2014
Achieving spilling-friendly register file assignment for highly distributed register files.
J. Supercomput., 2014

Register spilling via transformed interference equations for PAC DSP architecture.
Concurr. Comput. Pract. Exp., 2014

2012
Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files.
J. Supercomput., 2012

2011
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.
J. Signal Process. Syst., 2011

2010
Programming model and tools for embedded multicore systems.
Int. J. Embed. Syst., 2010

2008
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.
J. Signal Process. Syst., 2008

2006
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

2005
Compiler Supports and Optimizations for PAC VLIW DSP Processors.
Proceedings of the Languages and Compilers for Parallel Computing, 2005


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