Chung-Hsun Huang
Orcid: 0000-0002-5378-2670
According to our database1,
Chung-Hsun Huang
authored at least 25 papers
between 2000 and 2023.
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On csauthors.net:
Bibliography
2023
Design and Implementation of Machine Tool Life Inspection System Based on Sound Sensing.
Sensors, 2023
2020
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the ICCBN 2020: 8th International Conference on Communications and Broadband Networking, 2020
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020
2018
Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018
2016
An area and power efficient adder-based stepwise linear interpolation for digital signal processing.
IEEE Trans. Consumer Electron., 2016
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEICE Electron. Express, 2014
IEICE Electron. Express, 2014
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET).
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
IEICE Electron. Express, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Low power and cost effective scaling engine with locking frame rate for display controllers.
IEEE Trans. Consumer Electron., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A fast and high efficiency buck converter with Switch-On-Demand Modulator for wide load range applications.
IEICE Electron. Express, 2011
A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2004
2003
IEEE J. Solid State Circuits, 2003
2002
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques.
IEEE J. Solid State Circuits, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000