Chung-Ching Peng
Orcid: 0009-0001-5944-4146
According to our database1,
Chung-Ching Peng
authored at least 5 papers
between 2009 and 2024.
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Collaborative distances:
Timeline
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2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization.
Proceedings of the 2024 International Symposium on Physical Design, 2024
2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019
2018
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009