Chung-An Shen
Orcid: 0000-0002-0628-5129
According to our database1,
Chung-An Shen
authored at least 59 papers
between 2010 and 2024.
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Bibliography
2024
Design and Implementation of a Multiconnectivity IoT Modem for Highly Reliable Consumer Applications.
IEEE Consumer Electron. Mag., September, 2024
The Algorithm and VLSI Architecture of High-Throughput and Highly Efficient Tensor Decomposition Engine.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
IEEE J. Sel. Areas Commun., September, 2023
The Design of Efficient Data Flow and Low-Complexity Architecture for a Highly Configurable CNN Accelerator.
Circuits Syst. Signal Process., August, 2023
The design of a configurable and low-latency packet parsing system for communication networks.
Telecommun. Syst., April, 2023
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
The Data Flow and Architectural Optimizations for a Highly Efficient CNN Accelerator Based on the Depthwise Separable Convolution.
Circuits Syst. Signal Process., 2022
A New Tracking-Attack Scenario Based on the Vulnerability and Privacy Violation of 5G AKA Protocol.
IEEE Access, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Momentum-based ICA for Self Interference Cancellation in In-Band Full-Duplex Systems.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems.
J. Signal Process. Syst., 2021
The Design and Implementation of a Highly Efficient and Low-Complexity Joint-MMSE GFDM Receiver.
J. Signal Process. Syst., 2021
An integrated multi-controller management framework for highly reliable software defined networking.
Telecommun. Syst., 2021
IEEE Open J. Commun. Soc., 2021
The Algorithm and VLSI Architecture of an Efficient Image Sharpening Scheme Based on the Frequency Domain Analysis.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021
Independent Component Analysis with Nonlinearity Mitigation for MIMO Full-Duplex Systems.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
The Configurable Hybrid Precoding Processor for Bit-Stream-Based mmWave MIMO Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Novel Routing Algorithm for the Acceleration of Flow Scheduling in Time-Sensitive Networks.
Sensors, 2020
The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems.
Circuits Syst. Signal Process., 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder.
J. Real Time Image Process., 2019
The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems.
J. Real Time Image Process., 2019
Proceedings of the 90th IEEE Vehicular Technology Conference, 2019
An Efficient Joint Node and Link Mapping Approach Based on Genetic Algorithm for Network Virtualization.
Proceedings of the 90th IEEE Vehicular Technology Conference, 2019
Proceedings of the 90th IEEE Vehicular Technology Conference, 2019
Proceedings of the ACM MobiHoc Workshop on Pervasive Systems in the IoT Era, 2019
The Design and Implementation of a Highly Efficient Motion Estimation Engine for HEVC Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Programmable and FPGA-accelerated GTP Offloading Engine for Mobile Edge Computing in 5G Networks.
Proceedings of the IEEE INFOCOM 2019, 2019
2018
Advanced Multimedia Power-Saving Method Using a Dynamic Pixel Dimmer on AMOLED Displays.
IEEE Trans. Circuits Syst. Video Technol., 2018
The hardware and software co-design of a configurable QoS for video streaming based on OpenFlow protocol and NetFPGA platform.
Multim. Tools Appl., 2018
Design and implementation of a high-throughput configurable pre-processor for MIMO detections.
Microelectron. J., 2018
Architectural Optimizations for a High-Throughput Sorted QR Decomposition Circuit in MIMO Communication Systems.
J. Circuits Syst. Comput., 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA.
Proceedings of the VII International Conference on Network, Communication and Computing, 2018
The Hardware and Software Co-Design of a Stackable OpenFlow Switch for Software Defined Networking.
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
A Real-time and Memory-saving Link Recovery Mechanism for Green Software-Defined Networking.
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
2017
IEEE Trans. Circuits Syst. Video Technol., 2017
The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections.
Proceedings of the 36th IEEE International Performance Computing and Communications Conference, 2017
A high performance media server and QoS routing for SVC streaming based on Software-Defined Networking.
Proceedings of the 2017 International Conference on Computing, 2017
2016
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2016
The design and implementation of a configurable MIMO detection system on the NOC-based multicore platform.
Microelectron. J., 2016
Tree search based configurable joint detection and decoding algorithms for MIMO systems.
Proceedings of the 2016 International Conference on Computing, 2016
Design and implementation of a low-latency, high-throughput sorted QR decomposition circuit for MIMO communications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
2014
Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A high-throughput interpolator for fractional motion estimation in high efficient video coding (HEVC) systems.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 × 4 64-QAM System.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Joint Detection and Decoding for MIMO Systems Using Convolutional Codes: Algorithm and VLSI Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE Global Communications Conference, 2012
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 7th IEEE Consumer Communications and Networking Conference, 2010