Chune-Sin Yeh

According to our database, Chune-Sin Yeh authored at least 3 papers between 1990 and 2000.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2000

GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.

Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Gate-level aged timing simulation methodology for hot-carrier reliability assurance.

Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu

Proceedings of ASP-DAC 2000, 2000

1990

NASFLOW, a Simulation Tool for Silicon Technology Development.

D. David Forsythe, Atul P. Agarwal, Chune-Sin Yeh, Sheldon Aronowitz, Bhaskar Gadepally

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990