Chun-Nan Liu

According to our database, Chun-Nan Liu authored at least 18 papers between 2003 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Multi-core system performance prediction and analysis at the ESL.

Jen-Chieh Yeh, Chi-Hung Lin, Chun-Nan Liu

Int. J. Comput. Sci. Eng., 2014

2013

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.

Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Baseband design and software-defined-radio implementation for LTE femtocell.

Dung-Rung Hsieh, De-Jhen Huang, Jen-Yuan Hsu, Chieh-Yu Kao, Ming-Che Lin, Chun-Nan Liu, Pangan Ting

Proceedings of the 9th Asian Control Conference, 2013

2012

Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.

Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming.

Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, An-Yeu Wu

J. Signal Process. Syst., 2011

Parallel Integral Image Generation Algorithm on Multi-core System.

Yi-Ta Wu, Yih-Tyng Wu, Chao-Yi Cho, Shau-Yin Tseng, Chun-Nan Liu, Chung-Ta King

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

Real-Time Photo Sensor Dead Pixel Detection for Embedded Devices.

Chao-Yi Cho, Tse-Min Chen, Wen-Shan Wang, Chun-Nan Liu

Proceedings of the 2011 International Conference on Digital Image Computing: Techniques and Applications (DICTA), 2011

System-level design exploration for 3-D stacked memory architectures.

Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2009

Low-Power System Design for MPEG-2/4 AAC Audio Decoder Using Pure ASIC Approach.

Tsung-Han Tsai, Chun-Nan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 1.4 MHz 0.21 mW MPEG-2/4 AAC single chip decoder.

Tsung-Han Tsai, Chun-Nan Liu, Hsueh-Yi Lin, Hsing-Chuang Liu, Chia-Ying Wu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards.

Tsung-Han Tsai, Chun-Nan Liu

J. Signal Process. Syst., 2008

VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor.

Tsung-Han Tsai, Chun-Nan Liu, Jui Hong Hung

IEEE Trans. Consumer Electron., 2008

Optimization techniques of AAC decoder on PACDSP VLIW processor.

Chun-Nan Liu, Jui Hong Hung, Tsung-Han Tsai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Configurable Common Filterbank Processor for Multi-Standard Audio Decoder.

Tsung-Han Tsai, Chun-Nan Liu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2005

A Hardware/Software Co-Design of MP3 Audio Decoder.

Tsung-Han Tsai, Ya-Chau Yang, Chun-Nan Liu

J. VLSI Signal Process., 2005

A hardware/software co-design case study on MPEG AAC audio decoder.

Tsung-Han Tsai, Chun-Nan Liu

Int. J. Embed. Syst., 2005

SoC platform based design of MPEG-2/4 AAC audio decoder.

Chun-Nan Liu, Tsung-Han Tsai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

A low power VLSI implementation for variable length decoder in MPEG-1 layer III.

Tsung-Han Tsai, Wen-Cheng Chen, Chun-Nan Liu

Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003