Chun-Ming Hsu
According to our database1,
Chun-Ming Hsu
authored at least 16 papers
between 2008 and 2022.
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Bibliography
2022
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and Systems.
IEEE Open J. Circuits Syst., 2021
Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the European Conference on Optical Communication, 2021
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012
2009
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop.
IEEE J. Solid State Circuits, 2009
2008
PhD thesis, 2008
A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation.
IEEE J. Solid State Circuits, 2008
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008