Chun Jason Xue

Orcid: 0000-0002-6431-9868

Affiliations:
  • Mohamed bin Zayed University of Artificial Intelligence (MBZUAI), Abu Dhabi, United Arab Emirates
  • City University of Hong Kong, Department of Computer Science, Kowloon, Hong Kong (former)
  • University of Texas at Dallas, Richardson, TX, USA (PhD 2007)


According to our database1, Chun Jason Xue authored at least 400 papers between 2004 and 2024.

Collaborative distances:

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Bibliography

2024
Extremely-Compressed SSDs with I/O Behavior Prediction.
ACM Trans. Storage, November, 2024

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories.
ACM Trans. Archit. Code Optim., September, 2024

Efficient Time-Series Data Delivery in IoT With Xender.
IEEE Trans. Mob. Comput., May, 2024

Branch Predictor Design for Energy Harvesting Powered Nonvolatile Processors.
IEEE Trans. Computers, March, 2024

Flexible and Efficient Memory Swapping Across Mobile Devices With LegoSwap.
IEEE Trans. Parallel Distributed Syst., January, 2024

SHAP-CAT: A interpretable multi-modal framework enhancing WSI classification via virtual staining and shapley-value-based multimodal fusion.
CoRR, 2024

Advances in Multiple Instance Learning for Whole Slide Image Analysis: Techniques, Challenges, and Future Directions.
CoRR, 2024

Retrieval-Augmented Generation for Natural Language Processing: A Survey.
CoRR, 2024

Grade Like a Human: Rethinking Automated Assessment with Large Language Models.
CoRR, 2024

BehaviorGPT: Smart Agent Simulation for Autonomous Driving with Next-Patch Prediction.
CoRR, 2024

RAEE: A Training-Free Retrieval-Augmented Early Exiting Framework for Efficient Inference.
CoRR, 2024

IHC Matters: Incorporating IHC analysis to H&E Whole Slide Image Analysis for Improved Cancer Grading via Two-stage Multimodal Bilinear Pooling Fusion.
CoRR, 2024

Pre-processing matters: A segment search method for WSI classification.
CoRR, 2024

On the Compressibility of Quantized Large Language Models.
CoRR, 2024

Improving Natural Language Understanding with Computation-Efficient Retrieval Representation Fusion.
CoRR, 2024

An auction approach to aircraft bandwidth scheduling in non-terrestrial networks.
Comput. Networks, 2024

Binary Folding Compression for Efficient Software Distribution.
Proceedings of the 39th ACM/SIGAPP Symposium on Applied Computing, 2024

Timely Fusion of Surround Radar/Lidar for Object Detection in Autonomous Driving Systems.
Proceedings of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2024

RTiL: Real-Time Inference of Large Language Models on Memory-Constrained GPU Devices.
Proceedings of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2024

Reliability Impacts Among Neighboring Wordlines on 3D QLC NAND Flash.
Proceedings of the 13th Non-Volatile Memory Systems and Applications Symposium, 2024

Personalized Federated Learning with Auction-Based Client Selection and Edge-Enhanced Model Accuracy.
Proceedings of the International Joint Conference on Neural Networks, 2024

ReFusion: Improving Natural Language Understanding with Computation-Efficient Retrieval Representation Fusion.
Proceedings of the Twelfth International Conference on Learning Representations, 2024

STEM: Streaming-Based FPGA Acceleration for Large-Scale Compactions in LSM KV.
Proceedings of the 40th IEEE International Conference on Data Engineering, 2024

An Online Auction Approach to UAV Scheduling and Trajectory Planning.
Proceedings of the IEEE International Conference on Communications, 2024

Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Is Low Similarity Threshold A Bad Idea in Delta Compression?
Proceedings of the 16th ACM Workshop on Hot Topics in Storage and File Systems, 2024

When Compression Meets Model Compression: Memory-Efficient Double Compression for Large Language Models.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2024, 2024

CHESS: Optimizing LLM Inference via Channel-Wise Thresholding and Selective Sparsification.
Proceedings of the 2024 Conference on Empirical Methods in Natural Language Processing, 2024

LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND Flash.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Achieving Near-Zero Read Retry for 3D NAND Flash Memory.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

More Apps, Faster Hot-Launch on Mobile Devices via Fore/Background-aware GC-Swap Co-design.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

Palantir: Hierarchical Similarity Detection for Post-Deduplication Delta Compression.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

wearMeter: an Accurate Wear Metric for NAND Flash Memory.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Access Characteristic Guided Partition for Nand Flash-Based High-Density SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Pipette: Efficient Fine-Grained Reads for SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Effective Stack Wear Leveling for NVM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Efficient Real-time Video Conferencing with Adaptive Frame Delivery.
Comput. Networks, October, 2023

Optimizing Worst Case Data Freshness in RF-Powered Networked Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Variational Nested Dropout.
IEEE Trans. Pattern Anal. Mach. Intell., August, 2023

V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent Memory.
IEEE Trans. Computers, April, 2023

Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Meili: Enabling SmartNIC as a Service in the Cloud.
CoRR, 2023

2D-Empowered 3D Object Detection on the Edge.
CoRR, 2023

Poster: Meili: Towards SmartNIC as a Service.
Proceedings of the ACM SIGCOMM 2023 Conference, 2023

Worst-Case Latency Analysis of Message Synchronization in ROS.
Proceedings of the IEEE Real-Time Systems Symposium, 2023

Shared Dictionary Compression for Efficient Mobile Software Distribution.
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023

Read Disturb and Reliability: The Complete Story for 3D CT NAND Flash.
Proceedings of the 12th Non-Volatile Memory Systems and Applications Symposium, 2023

Retrieval-Augmented Multiple Instance Learning.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Modeling and Property Analysis of the Message Synchronization Policy in ROS.
Proceedings of the IEEE International Conference on Mobility, 2023

Moby: Empowering 2D Models for Efficient Point Cloud Analytics on the Edge.
Proceedings of the 31st ACM International Conference on Multimedia, 2023

Cross-Camera Inference on the Constrained Edge.
Proceedings of the IEEE INFOCOM 2023, 2023

Bayes-MIL: A New Probabilistic Perspective on Attention-based Multiple Instance Learning for Whole Slide Images.
Proceedings of the Eleventh International Conference on Learning Representations, 2023

Multi-Granularity Shadow Paging with NVM Write Optimization for Crash-Consistent Memory-Mapped I/O.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

ADOC: Automatically Harmonizing Dataflow Between Components in Log-Structured Key-Value Stores for Improved Performance.
Proceedings of the 21st USENIX Conference on File and Storage Technologies, 2023

ICE: Collaborating Memory and Process Management for User Experience on Resource-limited Mobile Devices.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023

SERICO: Scheduling Real-Time I/O Requests in Computational Storage Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Faster and Stronger Lossless Compression with Optimized Autoregressive Framework.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Work or Sleep: Freshness-Aware Energy Scheduling for Wireless Powered Communication Networks with Interference Consideration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Introduction to the Special Issue on Accelerating AI on the Edge - Part 2.
ACM Trans. Embed. Comput. Syst., November, 2022

Introduction to the Special Issue on Accelerating AI on the Edge - Part 1.
ACM Trans. Embed. Comput. Syst., September, 2022

ScaleFlux: Efficient Stateful Scaling in NFV.
IEEE Trans. Parallel Distributed Syst., 2022

Reprogramming 3D TLC Flash Memory based Solid State Drives.
ACM Trans. Storage, 2022

NetKernel: Making Network Stack Part of the Virtualized Infrastructure.
IEEE/ACM Trans. Netw., 2022

Accelerating Monte Carlo Bayesian Prediction via Approximating Predictive Uncertainty Over the Simplex.
IEEE Trans. Neural Networks Learn. Syst., 2022

Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Resolving the Reliability Issues of Open Blocks for 3-D NAND Flash: Observations and Strategies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Throughput Maximization in Wireless Communication Systems Powered by Hybrid Energy Harvesting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Bits-Ensemble: Toward Light-Weight Robust Deep Ensemble by Bits-Sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Online Rare Category Identification and Data Diversification for Edge Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

NFL: Robust Learned Index via Distribution Transformation.
Proc. VLDB Endow., 2022

A Fast Transformer-based General-Purpose Lossless Compressor.
CoRR, 2022

Stop unnecessary refreshing: extending 3D NAND flash lifetime with ORBER.
CCF Trans. High Perform. Comput., 2022

Read latency variation aware performance optimization on high-density NAND flash based storage systems.
CCF Trans. High Perform. Comput., 2022

TRACE: A Fast Transformer-based General-Purpose Lossless Compressor.
Proceedings of the WWW '22: The ACM Web Conference 2022, Virtual Event, Lyon, France, April 25, 2022

Accelerating General-purpose Lossless Compression via Simple and Scalable Parameterization.
Proceedings of the MM '22: The 30th ACM International Conference on Multimedia, Lisboa, Portugal, October 10, 2022

Probabilistic Analysis of Network Availability.
Proceedings of the 30th IEEE International Conference on Network Protocols, 2022

Alfie: Neural-Reinforced Adaptive Prefetching for Short Videos.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2022

Message from ICESS 2022 General Chairs.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

$p$LPAQ: Accelerating LPAQ Compression on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2022

CacheSifter: Sifting Cache Files for Boosted Mobile Performance and Lifetime.
Proceedings of the 20th USENIX Conference on File and Storage Technologies, 2022

PipeDevice: a hardware-software co-design approach to intra-host container communication.
Proceedings of the 18th International Conference on emerging Networking EXperiments and Technologies, 2022

Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Read-Ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization.
IEEE Trans. Computers, 2021

Accelerating data filtering for database using FPGA.
J. Syst. Archit., 2021

Bayesian Nested Neural Networks for Uncertainty Calibration and Adaptive Compression.
CoRR, 2021

Composite Resource Scheduling for Networked Control Systems.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Keep Fresh: Real-Time Data Retrieval with Speed Adaptation in Mobile Cyber-Physical Systems.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Two-Dimensional Learning Rate Decay: Towards Accurate Federated Learning with Non-IID Data.
Proceedings of the International Joint Conference on Neural Networks, 2021

How the common retention acceleration method of 3D NAND flash memory goes wrong?
Proceedings of the HotStorage '21: 13th ACM Workshop on Hot Topics in Storage and File Systems, 2021

SFP: Smart File-Aware Prefetching for Flash based Storage Systems.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Pattern-Guided File Compression with User-Experience Enhancement for Log-Structured File System on Mobile Devices.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

MobileSwap: Cross-Device Memory Swapping for Mobile Devices.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Bayesian Nested Neural Networks for Uncertainty Calibration and Adaptive Compression.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems.
Proceedings of the APSys '21: 12th ACM SIGOPS Asia-Pacific Workshop on Systems, 2021

2020
Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory.
IEEE Trans. Reliab., 2020

Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism.
IEEE Trans. Parallel Distributed Syst., 2020

Inspection and Characterization of App File Usage in Mobile Devices.
ACM Trans. Storage, 2020

Applying Multiple Level Cell to Non-volatile FPGAs.
ACM Trans. Embed. Comput. Syst., 2020

Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SEAL: User Experience-Aware Two-Level Swap for Mobile Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Aging Capacitor Supported Cache Management Scheme for Solid-State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Maximizing I/O Throughput and Minimizing Performance Variation via Reinforcement Learning Based I/O Merging for SSDs.
IEEE Trans. Computers, 2020

Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory.
IEEE Trans. Computers, 2020

Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems.
J. Syst. Archit., 2020

Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs.
ACM J. Emerg. Technol. Comput. Syst., 2020

Acclaim: Adaptive Memory Reclaim to Improve User Experience in Android Systems.
Proceedings of the 2020 USENIX Annual Technical Conference, 2020

Maintaining Real-Time Data Freshness in Wireless Powered Communication Networks.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

A Zero-Energy Consumption Scheme for System Suspend to Limited NVM.
Proceedings of the 9th Non-Volatile Memory Systems and Applications Symposium, 2020

Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Fully Nested Neural Network for Adaptive Compression and Quantization.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

FPGA-based Compaction Engine for Accelerating LSM-tree Key-Value Stores.
Proceedings of the 36th IEEE International Conference on Data Engineering, 2020

Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Overcoming Memory Constraint for Improved Target Classification Performance on Embedded Deep Learning Systems.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

Position: Synergetic effects of Software and Hardware Parameters on the LSM system.
Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

Differentiating Cache Files for Fine-grain Management to Improve Mobile Performance and Lifetime.
Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
File Fragmentation in Mobile Devices: Measurement, Evaluation, and Treatment.
IEEE Trans. Mob. Comput., 2019

A Hardware-Accelerated Solution for Hierarchical Index-Based Merge-Join.
IEEE Trans. Knowl. Data Eng., 2019

Real-Time Data Retrieval in Cyber-Physical Systems with Temporal Validity and Data Availability Constraints.
IEEE Trans. Knowl. Data Eng., 2019

Introduction to the Special Issue on Human-interaction-aware Data Analytics for Cyber-physical Systems.
ACM Trans. Cyber Phys. Syst., 2019

Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

EMC: Energy-Aware Morphable Cache Design for Non-Volatile Processors.
IEEE Trans. Computers, 2019

Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory.
IEEE Trans. Computers, 2019

Boosting read-ahead efficiency for improved user experience on mobile devices.
SIGBED Rev., 2019

BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors.
Microelectron. J., 2019

A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices.
IEEE Micro, 2019

luXbeacon - A Batteryless Beacon for Green IoT: Design, Modeling, and Field Tests.
IEEE Internet Things J., 2019

Accelerating Monte Carlo Bayesian Inference via Approximating Predictive Uncertainty over Simplex.
CoRR, 2019

Checkpointing-aware Data Allocation for Energy Harvesting Powered Non-volatile Processors.
Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.
Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Optimizing Tail Latency of LDPC based Flash Memory Storage Systems Via Smart Refresh.
Proceedings of the 2019 IEEE International Conference on Networking, 2019

Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019

Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

1+1>2: variation-aware lifetime enhancement for embedded 3D NAND flash systems.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Reinforcement Learning based Background Segment Cleaning for Log-structured File System on Mobile Devices.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

A Hardware-Accelerated Solution for Hierarchical Index-Based Merge-Join(Extended Abstract).
Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Mismatched Memory Management of Android Smartphones.
Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019

Sentinel Cells Enabled Fast Read for NAND Flash.
Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019

A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Online Rare Category Detection for Edge Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Transmit or Discard: Optimizing Data Freshness in Networked Embedded Systems with Energy Harvesting Sources.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Leveraging Approximate Data for Robust Flash Storage.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Wear-Leveling-Aware Fine-Grained Allocator for Non-Volatile Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

PreGC: Pre-migrating valid pages to relieve performance cliff of 3D solid-state drives: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Introduction to the Special Issue on NVM and Storage.
ACM Trans. Storage, 2018

Avoiding Data Inconsistency in Energy Harvesting Powered Embedded Systems.
ACM Trans. Design Autom. Electr. Syst., 2018

Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs.
ACM Trans. Design Autom. Electr. Syst., 2018

Guest Editorial Circuit and System Design Automation for Internet of Things.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems.
IEEE Trans. Computers, 2018

Energy Optimal Task Scheduling with Normally-Off Local Memory and Sleep-Aware Shared Memory with Access Conflict.
IEEE Trans. Computers, 2018

Race to idle or not: balancing the memory sleep time with DVS for energy minimization.
J. Comb. Optim., 2018

Survey of Low-Power Electric Vehicles: A Design Automation Perspective.
IEEE Des. Test, 2018

EasyConvPooling: Random Pooling with Easy Convolution for Accelerating Training and Testing.
CoRR, 2018

Work-in-Progress: Joint Network and Computing Resource Scheduling for Wireless Networked Control Systems.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

F2FS Aware Mapping Cache Design on Solid State Drives.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

NVLH: Crash-Consistent Linear Hashing for Non-Volatile Memory.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

Shadow Block: Accelerating ORAM Accesses with Data Duplication.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Selective Compression Scheme for Read Performance Improvement on Flash Devices.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Near Data Filtering for Distributed Database Systems.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

An Efficient Cache Management Scheme for Capacitor Equipped Solid State Drives.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

Maximizing I/O throughput and minimizing performance variation via reinforcement learning based I/O merging for SSDs: work-in-progress.
Proceedings of the International Conference on Compilers, 2018

Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM code.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Emerging and Nonvolatile Memory.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2017

DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Maximizing Common Idle Time on Multicore Processors With Shared Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Guest Editorial: Special Issue on Embedded Computing for IoT.
ACM Trans. Embed. Comput. Syst., 2017

Lightweight Data Compression for Mobile Flash Storage.
ACM Trans. Embed. Comput. Syst., 2017

Guest Editorial: Special Issue on LCTES 2015.
ACM Trans. Embed. Comput. Syst., 2017

State Asymmetry Driven State Remapping in Phase Change Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Memory-Aware Embedded Control Systems Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.
IEEE Trans. Computers, 2017

Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)".
Microprocess. Microsystems, 2017

Data re-allocation enabled cache locking for embedded systems.
J. Syst. Archit., 2017

Improving File System Performance of Mobile Storage Systems Using a Decoupled Defragmenter.
Proceedings of the 2017 USENIX Annual Technical Conference, 2017

Energy-aware morphable cache management for self-powered non-volatile processors.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

An empirical study of F2FS on mobile devices.
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017

Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

Enhancing SSD performance with LDPC-aware garbage collection.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Design Exploration for Multiple Level Cell Based Non-Volatile FPGAs.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors.
Proceedings of the 54th Annual Design Automation Conference, 2017

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement.
Proceedings of the 54th Annual Design Automation Conference, 2017

A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

On efficient message passing in energy harvesting based distributed system.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Improving LDPC performance via asymmetric sensing level placement on flash memory.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems.
IEEE Trans. Multi Scale Comput. Syst., 2016

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems.
IEEE Trans. Computers, 2016

Write reconstruction for write throughput improvement on MLC PCM based main memory.
J. Syst. Archit., 2016

Redesigning software and systems for non-volatile processors on self-powered devices.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.
Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Energy-Aware Real-Time Task Scheduling on Local/Shared Memory Systems.
Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

Dynamic merging/splitting for better responsiveness in mobile devices.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Refresh-aware loop scheduling for high performance low power volatile STT-RAM.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

An Empirical Study of File-System Fragmentation in Mobile Storage Systems.
Proceedings of the 8th USENIX Workshop on Hot Topics in Storage and File Systems, 2016

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

I/O scheduling with mapping cache awareness for flash based storage systems.
Proceedings of the 2016 International Conference on Embedded Software, 2016

Exploiting process variation for retention induced refresh minimization on flash memory.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016

HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Accurate personal ultraviolet dose estimation with multiple wearable sensors.
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Joint WCET and Update Activity Minimization for Cyber-Physical Systems.
ACM Trans. Embed. Comput. Syst., 2015

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.
IEEE Trans. Computers, 2015

Modular Performance Analysis of Energy-Harvesting Real-Time Networked Systems.
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

C3: Cooperative Code Positioning and Cache Locking for WCET Minimization.
Proceedings of the 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2015

Improving MLC PCM write throughput by write reconstruction.
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing IO performance via conflict reduction for flash memory storage systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing common idle time on multi-core processors with shared memory.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Race to idle or not: balancing the memory sleep time with DVS for energy minimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Compiler directed automatic stack trimming for efficient non-volatile processors.
Proceedings of the 52nd Annual Design Automation Conference, 2015

DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-powered wearable sensor node: Challenges and opportunities.
Proceedings of the 2015 International Conference on Compilers, 2015

Minimizing MLC PCM write energy for free through profiling-based state remapping.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Unified Write Buffer Cache Management Scheme for Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols.
IEEE Trans. Parallel Distributed Syst., 2014

Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2014

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors.
ACM Trans. Embed. Comput. Syst., 2014

Error Model Guided Joint Performance and Endurance Optimization for Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories.
IEEE Trans. Computers, 2014

Dual partitioning multicasting for high-performance on-chip networks.
J. Parallel Distributed Comput., 2014

Non-volatile registers aware instruction selection for embedded systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Register allocation for hybrid register architecture in nonvolatile processors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A wear-leveling-aware dynamic stack for PCM memory in embedded systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Retention Trimming for Wear Reduction of Flash Memory Storage Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Algorithms to Minimize Data Transfer for Code Update on Wireless Sensor Network.
J. Signal Process. Syst., 2013

Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory.
IEEE Trans. Signal Process., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.
ACM Trans. Design Autom. Electr. Syst., 2013

Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures.
ACM Trans. Embed. Comput. Syst., 2013

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.
ACM Trans. Embed. Comput. Syst., 2013

Write activity reduction on non-volatile main memories for embedded chip multiprocessors.
ACM Trans. Embed. Comput. Syst., 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
SIGBED Rev., 2013

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory.
J. Syst. Archit., 2013

Data re-allocation enabled cache locking for embedded systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Compiler directed write-mode selection for high performance low power volatile PCM.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

Profit maximization through process variation aware high level synthesis with speed binning.
Proceedings of the Design, Automation and Test in Europe, 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.
Proceedings of the Design, Automation and Test in Europe, 2013

Software enabled wear-leveling for hybrid PCM main memory on embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Multirate controller design for resource- and schedule-constrained automotive ECUs.
Proceedings of the Design, Automation and Test in Europe, 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Minimizing code size via page selection optimization on partitioned memory architectures.
Proceedings of the International Conference on Compilers, 2013

WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Instruction Cache Locking for Embedded Systems using Probability Profile.
J. Signal Process. Syst., 2012

Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling.
IEEE Trans. Signal Process., 2012

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems.
ACM Trans. Design Autom. Electr. Syst., 2012

Single and multiple device DSA problems, complexities and online algorithms.
Theor. Comput. Sci., 2012

Instruction cache locking for multi-task real-time embedded systems.
Real Time Syst., 2012

Loop fusion and reordering for register file optimization on stream processors.
J. Syst. Softw., 2012

Register allocation for write activity minimization on non-volatile main memory for embedded systems.
J. Syst. Archit., 2012

Memory access schedule minimization for embedded systems.
J. Syst. Archit., 2012

Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.
J. Comb. Optim., 2012

General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size.
Int. J. Comput. Their Appl., 2012

Guest Editorial Special Section on Memory Architectures and Organization.
IEEE Embed. Syst. Lett., 2012

Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2012

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Poster Abstract: Smart Phone Lift for Improving Energy Efficiency and User Comfort in Green Buildings.
Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012

Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PRR: A low-overhead cache replacement algorithm for embedded processors.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory.
Proceedings of the 16th Workshop on Interaction between Compilers and Computer Architectures, 2012

2011
Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability.
J. Parallel Distributed Comput., 2011

Sleep-aware mode assignment in wireless embedded systems.
J. Parallel Distributed Comput., 2011

Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC.
J. Parallel Distributed Comput., 2011

Acceleration of Composite Order Bilinear Pairing on Graphics Hardware.
IACR Cryptol. ePrint Arch., 2011

STT-RAM based energy-efficiency hybrid cache for CMPs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

Optimal task allocation on non-volatile memory based hybrid main memory.
Proceedings of the Research in Applied Computation Symposium, 2011

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

ExLRU: a unified write buffer cache management for flash memory.
Proceedings of the 11th International Conference on Embedded Software, 2011

Register allocation for simultaneous reduction of energy and peak temperature on registers.
Proceedings of the Design, Automation and Test in Europe, 2011

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory.
Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Optimizing Memory Cost with Loop Transformations.
Proceedings of the ISCA 26th International Conference on Computers and Their Applications, 2011

Register allocation for write activity minimization on non-volatile main memory.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Variable Length Pattern Matching for Hardware Network Intrusion Detection System.
J. Signal Process. Syst., 2010

Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding.
ACM Trans. Embed. Comput. Syst., 2010

Fine-grained adaptive CMP cache sharing through access history exploitation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Optimal scheduling to minimize non-volatile memory access time with hardware cache.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Minimizing write activities to non-volatile memory via scheduling and recomputation.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Single and Multiple Device DSA Problem, Complexities and Online Algorithms.
Proceedings of the Algorithms and Computation - 21st International Symposium, 2010

Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC.
Proceedings of the 39th International Conference on Parallel Processing, 2010

LADPM: Latency-Aware Dual-Partition Multicast Routing for Mesh-Based Network-on-Chips.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Write activity reduction on flash main memory via smart victim cache.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation.
Proceedings of the 47th Design Automation Conference, 2010

Energy efficient joint scheduling and multi-core interconnect design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.
J. Signal Process. Syst., 2009

Optimizing scheduling and intercluster connection for application-specific DSP processors.
IEEE Trans. Signal Process., 2009

Loop scheduling and bank type assignment for heterogeneous multi-bank memory.
J. Parallel Distributed Comput., 2009

Optimizing parallelism for nested loops with iterational and instructional retiming.
J. Embed. Comput., 2009

Energy minimization for heterogeneous wireless sensor networks.
J. Embed. Comput., 2009

Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking.
Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009

Reprogramming with Minimal Transferred Data on Wireless Sensor Network.
Proceedings of the IEEE 6th International Conference on Mobile Adhoc and Sensor Systems, 2009

Minimizing Memory Access Schedule for Memories.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems.
Proceedings of the 29th IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2009 Workshops), 2009

Loop Fusion Technique with Minimal Memory Cost via Retiming.
Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

Energy-aware register file re-partitioning for clustered VLIW architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Computation and data transfer co-scheduling for interconnection bus minimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Timing optimization via nest-loop pipelining considering code size.
Microprocess. Microsystems, 2008

Minimizing Transferred Data for Code Update on Wireless Sensor Network.
Proceedings of the Wireless Algorithms, 2008

Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.
Proceedings of the Distributed Embedded Systems: Design, 2008

A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems.
Proceedings of the 28th IEEE International Conference on Distributed Computing Systems (ICDCS 2008), 2008

Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.
Proceedings of the IEEE International Conference on Acoustics, 2008

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.
Proceedings of the FPL 2008, 2008

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

QoS for Networked Heterogeneous Real-Time Embedded Systems.
Proceedings of the ISCA 21st International Conference on Parallel and Distributed Computing and Communication Systems, 2008

2007
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.
J. VLSI Signal Process., 2007

Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.
J. VLSI Signal Process., 2007

Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Parallel Network Intrusion Detection on Reconfigurable Platforms.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Loop scheduling with timing and switching-activity minimization for VLIW DSP.
ACM Trans. Design Autom. Electr. Syst., 2006

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.
IEEE Trans. Computers, 2006

Design optimization and space minimization considering timing and code size via retiming and unfolding.
Microprocess. Microsystems, 2006

Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.
J. Parallel Distributed Comput., 2006

Algorithms and analysis of scheduling for loops with minimum switching.
Int. J. Comput. Sci. Eng., 2006

Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Loop Striping: Maximize Parallelism for Nested Loops.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
Efficient Assignment and Scheduling for Heterogeneous DSP Systems.
IEEE Trans. Parallel Distributed Syst., 2005

Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Optimizing DSP scheduling via address assignment with array and loop transformation.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Optimizing Nested Loops with Iterational and Instructional Retiming.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Iterational retiming: maximize iteration-level parallelism for nested loops.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

High-level synthesis for DSP applications using heterogeneous functional units.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Multi-level Loop Fusion with Minimal Code Size.
Proceedings of the ISCA 18th International Conference on Parallel and Distributed Computing Systems, 2005

2004
Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Optimizing Address Assignment for Scheduling Embedded DSPs.
Proceedings of the Embedded and Ubiquitous Computing, 2004


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