Chun-Chuan Chi

According to our database, Chun-Chuan Chi authored at least 12 papers between 2009 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2014

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.

Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng

IEEE Des. Test, 2014

2013

3D-IC interconnect test, diagnosis, and repair.

Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.

Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree

J. Electron. Test., 2012

3D-IC BISR for stacked memories using cross-die spares.

Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu

Proceedings of the 2011 IEEE International Test Conference, 2011

DfT Architecture for 3D-SICs with Multiple Towers.

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu

Proceedings of the 16th European Test Symposium, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.

Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang

Proceedings of the 48th Design Automation Conference, 2011

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

A low-cost and scalable test architecture for multi-core chips.

Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li

Proceedings of the 15th European Test Symposium, 2010

3D DfT architecture for pre-bond and post-bond testing.

Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Test Integration for SOC Supporting Very Low-Cost Testers.

Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu

Proceedings of the Eighteentgh Asian Test Symposium, 2009