Chulhyun Park
Orcid: 0000-0001-8301-3955
According to our database1,
Chulhyun Park
authored at least 10 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process.
IEEE Access, 2024
2021
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
IEEE Trans. Instrum. Meas., 2020
IEEE Trans. Instrum. Meas., 2020
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier.
IEEE Trans. Circuits Syst., 2020
2019
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2010
IET Inf. Secur., 2010
Proceedings of the 7th IEEE Consumer Communications and Networking Conference, 2010
2009
Proceedings of the International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, 2009