Chulho Shin

According to our database1, Chulho Shin authored at least 16 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Z 2 traversal order: An interleaving approach for VR stereo rendering on tile-based GPUs.
Comput. Vis. Media, 2017

2016
Z<sup>2</sup> traversal order for VR stereo rendering on tile-based mobile GPUs.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Technical Briefs, 2016

AXAA: adaptive approximate anti-aliasing.
Proceedings of the Special Interest Group on Computer Graphics and Interactive Techniques Conference, 2016

Cost-effective frame rate control for mobile GPUs.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Posters, 2016

Effective stereoscopic rendering for mobile VR.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Posters, 2016

2015
Half frame forwarding: frame-rate up conversion for tiled rendering GPU.
Proceedings of the Special Interest Group on Computer Graphics and Interactive Techniques Conference, 2015

Dynamic rendering quality scaling for mobile GPU.
Proceedings of the SIGGRAPH Asia 2015 Posters, Kobe, Japan, November 2-6, 2015, 2015

Reusing MRTs for mobile GPUs.
Proceedings of the SIGGRAPH Asia 2015 Posters, Kobe, Japan, November 2-6, 2015, 2015

2011
Emulation based high-accuracy throughput estimation for high-speed connectivities: case study of USB2.0.
Proceedings of the 48th Design Automation Conference, 2011

2008
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.
Des. Autom. Embed. Syst., 2007

2006
Adaptive dynamic thread scheduling for simultaneous multithreaded architectures with a detector thread.
J. Parallel Distributed Comput., 2006

2005
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.
Proceedings of the 2005 Design, 2005

2004
The need for adaptive dynamic thread scheduling in simultaneous multithreading.
Parallel Process. Lett., 2004

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.
Proceedings of the 2004 Design, 2004

2003
Dynamic Scheduling Issues in SMT Architectures.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003


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