Chulbum Kim

Orcid: 0000-0002-6391-9423

According to our database¹, Chulbum Kim authored at least 8 papers between 2010 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Bibliography

2024

13.7 A 1Tb Density 3b/Cell 3D-NAND Flash on a 2YY-Tier Technology with a 300MB/s Write Throughput.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2018

A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2012

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

2010

A 159mm<sup>2</sup> 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Chulbum Kim

Timeline

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