Chuck Haymes
Orcid: 0000-0002-5056-3528
According to our database1,
Chuck Haymes
authored at least 10 papers
between 2006 and 2023.
Collaborative distances:
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Bibliography
2023
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2017
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2012
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2009
Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets.
IEEE Trans. Commun., 2009
2007
Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of IEEE International Conference on Communications, 2006