Chuanjun Zhang

Hongxing Liu

Bo Yang

Remote. Sens., 2020

The 3D Projection Function on NetPad.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Computer Science & Education, 2020

2016

The Beauty of Geometry: A touch-operation-based DGS for mathematics education.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computer Science & Education, 2016

2014

Exploiting natural redundancy in visual information.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A task-oriented vision system.

[BibT_eX]

[DOI]

Yang Xiao

Kevin M. Irick

Jack Sampson

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

EMERALD: Characterization of emerging applications and algorithms for low-power devices.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

WoM-SET: Low power proactive-SET-based PCM write using WoM code.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems.

[BibT_eX]

[DOI]

Yang Xiao

Kevin Inck

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Accelerators for biologically-inspired attention and recognition.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2010

A tag-based cache replacement.

[BibT_eX]

[DOI]

Bing Xue

Proceedings of the 28th International Conference on Computer Design, 2010

2009

Divide-and-conquer: a bubble replacement for low level caches.

[BibT_eX]

[DOI]

Bing Xue

Proceedings of the 23rd international conference on Supercomputing, 2009

2008

Reducing cache misses through programmable decoders.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

Two dimensional highly associative level-two cache design.

[BibT_eX]

[DOI]

Bing Xue

Proceedings of the 26th International Conference on Computer Design, 2008

2006

Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2006

Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Low Power Highly Associative Cache for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Reduce Register Files Leakage Through Discharging Cells.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

A highly configurable cache for low energy embedded systems.

[BibT_eX]

[DOI]

Walid A. Najjar

ACM Trans. Embed. Comput. Syst., 2005

Dynamic Co-allocation of Level One Caches.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

An efficient direct mapped instruction cache for application-specific embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004

Frequent value encoding for low power data buses.

[BibT_eX]

[DOI]

Jun Yang

Rajiv Gupta

ACM Trans. Design Autom. Electr. Syst., 2004

A self-tuning cache architecture for embedded systems.

[BibT_eX]

[DOI]

Roman L. Lysecky

ACM Trans. Embed. Comput. Syst., 2004

Low Static-Power Frequent-Value Data Caches.

[BibT_eX]

[DOI]

Jun Yang

Proceedings of the 2004 Design, 2004

Using a Victim Buffer in an Application-Specific Memory Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Tuning Caches to Applications for Low-Energy Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Highly configurable platforms for embedded computing systems.

[BibT_eX]

[DOI]

Microelectron. J., 2003

A Way-Halting Cache for Low-Energy High-Performance Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2003

Cache Configuration Exploration on Prototyping Platforms.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Energy Benefits of a Configurable Line Size Cache for Embedded Systems.

[BibT_eX]

[DOI]

Walid A. Najjar

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Highly-Configurable Cache Architecture for Embedded Systems.

[BibT_eX]

[DOI]

Walid A. Najjar

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

2002

A power-configurable bus for embedded systems.

[BibT_eX]

[DOI]