Chuanjin Richard Shi
Orcid: 0000-0002-3157-3464Affiliations:
- University of Washington, Department of Electrical Engineering, Seattle, WA, USA
- Fudan University, School of Microelectronics, China
According to our database1,
Chuanjin Richard Shi
authored at least 149 papers
between 1992 and 2024.
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Bibliography
2024
SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification.
IEEE Trans. Neural Networks Learn. Syst., September, 2024
Sensors, January, 2024
CoRR, 2024
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
IEEE Trans. Parallel Distributed Syst., September, 2023
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Augmenting aspect-level sentiment classification with distance-related local context input.
J. Supercomput., July, 2023
Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models.
CoRR, 2023
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
IEEE Trans. Hum. Mach. Syst., 2022
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain".
IEEE J. Solid State Circuits, 2022
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction.
Integr., 2022
The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition.
CoRR, 2022
A 0.021mm<sup>2</sup> 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain.
IEEE J. Solid State Circuits, 2021
A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the ICMLC 2021: 13th International Conference on Machine Learning and Computing, 2021
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2020
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits, 2020
Integr., 2020
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture.
IEEE Des. Test, 2020
The impact of real-time clinical alerts on the compliance of anesthesia documentation: A retrospective observational study.
Comput. Methods Programs Biomed., 2020
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Integr., 2018
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems.
Proceedings of the International SoC Design Conference, 2018
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the Computer Vision - ECCV 2018, 2018
Exploring the programmability for deep learning processors: from architecture to tensorization.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2013
Reducing the latency of Lee-O'Sullivan interpolation through modified initialization.
Proceedings of the 2013 Information Theory and Applications Workshop, 2013
2012
Proceedings of the 2012 Information Theory and Applications Workshop, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits.
Int. J. Circuit Theory Appl., 2010
Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2008
Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Integr., 2007
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
Proceedings of the 25th International Conference on Computer Design, 2007
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits.
Integr., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
An FPGA implementation of low-density parity-check code decoder with multi-rate capability.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Hierarchical extraction and verification of symmetry constraints for analog layout automation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.
Integr., 2003
Integr., 2003
Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Parametric Equivalent Circuit Extraction for VLSI Structures.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Efficient DDD-based term generation algorithm for analog circuit behavioral modeling.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
2001
Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 38th Design Automation Conference, 2001
2000
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the 2000 Design, 2000
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of ASP-DAC 2000, 2000
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis.
Proceedings of ASP-DAC 2000, 2000
1999
Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis.
ACM Trans. Design Autom. Electr. Syst., 1999
A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis.
Discret. Appl. Math., 1999
Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams.
Proceedings of the 1999 Design, 1999
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings.
Proceedings of the 36th Conference on Design Automation, 1999
Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
ACM Trans. Design Autom. Electr. Syst., 1998
Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
J. Electron. Test., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 1998 Design, 1998
Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Automatic Test Generation for Linear Analog Circuits under Parameter Variations.
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1995
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1992
Proceedings of the conference on European design automation, 1992