Chuan-Jia Jhang
According to our database1,
Chuan-Jia Jhang
authored at least 8 papers
between 2021 and 2024.
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Bibliography
2024
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.
IEEE J. Solid State Circuits, January, 2024
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021