Chua-Chin Wang
Orcid: 0000-0002-2426-2879
According to our database1,
Chua-Chin Wang
authored at least 257 papers
between 1994 and 2024.
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Bibliography
2024
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process.
Circuits Syst. Signal Process., June, 2024
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
Microelectron. J., 2024
Microelectron. J., 2024
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic.
Integr., 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.
Integr., May, 2023
Circuits Syst. Signal Process., April, 2023
IET Circuits Devices Syst., March, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion.
IEEE Trans. Neural Networks Learn. Syst., 2022
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process.
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Microelectron. J., 2021
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.
Microelectron. J., 2021
Circuits Syst. Signal Process., 2021
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process.
Circuits Syst. Signal Process., 2021
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer.
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
J. Signal Process. Syst., 2020
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst., 2020
A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry.
J. Circuits Syst. Comput., 2020
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.
J. Circuits Syst. Comput., 2020
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches<sup>*</sup>.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations.
Circuits Syst. Signal Process., 2019
A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the International Conference on IC Design and Technology, 2019
Proceedings of the International Conference on IC Design and Technology, 2019
A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology.
Proceedings of the International Conference on IC Design and Technology, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range.
Sensors, 2018
Circuits Syst. Signal Process., 2018
A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine.
Sensors, 2017
A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM.
Microelectron. J., 2017
Microelectron. J., 2017
Dynamic power estimation for ROM-less DDFS designs using switching activity analysis.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
A primary-side output current estimator with process compensator for flyback LED drivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Conference on Consumer Electronics, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IET Circuits Devices Syst., 2016
Proceedings of the International SoC Design Conference, 2016
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process.
Proceedings of the International SoC Design Conference, 2016
An accurate phase shift detector using bulk voltage boosting technique for sensing applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above.
Proceedings of the International Conference on IC Design and Technology, 2016
On-chip accurate primary-side output current estimator for flyback LED driver control.
Proceedings of the International Conference on IC Design and Technology, 2016
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
2015
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Microelectron. J., 2015
Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring.
Microelectron. J., 2015
Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology.
Microelectron. J., 2015
A wide range and high conversion gain power detector for frequency shift sensing applications.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard.
J. Signal Process. Syst., 2014
Noninvasive Control of the Power Transferred to an Implanted Device by an Ultrasonic Transcutaneous Energy Transfer Link.
IEEE Trans. Biomed. Eng., 2014
A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
An all-digital battery capacity monitor using calibrated current estimation approach.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique.
Sensors, 2013
Microelectron. J., 2013
Microelectron. J., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013
2012
A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers.
Microelectron. J., 2012
Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector.
Microelectron. J., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems.
Proceedings of the International SoC Design Conference, 2012
Feed-forward Output Swing Prediction AGC with Parallel-Detect Singular-Store Peak Detector.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
A high voltage analog multiplexer with digital calibration for battery management systems.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
A PLC transceiver design of in-vehicle power line in FlexRay-based automotive communication systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Linear programmable gain amplifier using reconfiguration local-feedback transconductors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
J. Signal Process. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Biomed. Circuits Syst., 2011
Microelectron. J., 2011
Microelectron. J., 2011
A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
J. Signal Process. Syst., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks.
IEICE Trans. Commun., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.
J. Signal Process. Syst., 2008
VLSI Design, 2008
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Biomed. Circuits Syst., 2008
A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants.
Microelectron. J., 2008
Microelectron. J., 2008
Microelectron. J., 2008
J. Circuits Syst. Comput., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
A self-disable sense technique with differential NAND cell for content-addressable memories.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator.
Microelectron. J., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Consumer Electron., 2006
An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Consumer Electron., 2005
IEEE Trans. Consumer Electron., 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
A 4-kB 500-MHz 4-T CMOS SRAM using low-V<sub>THN</sub> bitline drivers and high-V<sub>THP</sub> latches.
IEEE Trans. Very Large Scale Integr. Syst., 2004
High-PSR bias circuitry for NTSC sync separation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A phase-adjustable negative phase shifter using a single-shot locking method.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A C-less ASK demodulator for implantable neural interfacing chips.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
VLSI Design, 2002
An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method.
VLSI Design, 2002
IEEE Trans. Consumer Electron., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network.
J. Inf. Sci. Eng., 2001
A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems.
Comput. Commun., 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A 1.0 GHz clock generator design with a negative delay using a single-shot locking method.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
VLSI Design, 2000
Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library.
VLSI Design, 2000
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop.
VLSI Design, 2000
IEEE Trans. Syst. Man Cybern. Part A, 2000
IEEE J. Solid State Circuits, 2000
Inf. Sci., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
1999
Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Data compression by the recursive algorithm of exponential bidirectional associative memory.
IEEE Trans. Syst. Man Cybern. Part B, 1998
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998
1997
J. VLSI Signal Process., 1997
1996
Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory.
IEEE Trans. Syst. Man Cybern. Part B, 1996
Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory.
J. Inf. Sci. Eng., 1996
1995
The decision-making properties of discrete multiple exponential bidirectional associative memories.
IEEE Trans. Neural Networks, 1995
IEEE Trans. Neural Networks, 1995
Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Realization of bidirectional associative memory using a pseudo-parallel searching approach.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
1994