Chrysostomos Nicopoulos
Orcid: 0000-0001-6389-6068
According to our database1,
Chrysostomos Nicopoulos
authored at least 103 papers
between 2005 and 2024.
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Bibliography
2024
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.
IEEE Comput. Archit. Lett., 2024
IEEE Access, 2024
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Robustness of Artificial Neural Networks Based on Weight Alterations Used for Prediction Purposes.
Algorithms, July, 2023
IEEE Trans. Very Large Scale Integr. Syst., March, 2023
Microprocess. Microsystems, 2023
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Hardware-Assisted Heartbeat Mechanism for Fault Identification in Large-Scale IoT Systems.
IEEE Trans. Dependable Secur. Comput., 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching.
Integr., 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Practical Verifiable Computation by Using a Hardware-Based Correct Execution Environment.
IEEE Access, 2020
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
SmartFork: Partitioned Multicast Allocation and Switching in Network-on-Chip Routers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.
Microprocess. Microsystems, 2018
J. Electron. Test., 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Hardware-Based Online Self-Diagnosis for Faulty Device Identification in Large-Scale IoT Systems.
Proceedings of the 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation, 2018
2017
ACM Trans. Design Autom. Electr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
J. Parallel Distributed Comput., 2017
A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems.
J. Electr. Comput. Eng., 2017
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors.
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures.
ACM Trans. Archit. Code Optim., 2016
IEEE Comput. Archit. Lett., 2016
Powermax: an automated methodology for generating peak-power traffic in networks-on-chip.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Computers, 2015
HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Des. Autom. Embed. Syst., 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Exploration of system availability during software-based self-testing in many-core systems under test latency constraints.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era.
ACM Trans. Archit. Code Optim., 2013
Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing.
Parallel Comput., 2013
Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths.
IET Comput. Digit. Tech., 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting.
Proceedings of the 2012 Interconnection Network Architecture, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011
2010
Lecture Notes in Electrical Engineering 45, Springer, ISBN: 978-90-481-3030-6, 2010
IEEE Trans. Dependable Secur. Comput., 2010
Proceedings of the 28th International Conference on Computer Design, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
2008
Performance and power optimization through data compression in Network-on-Chip architectures.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
Proceedings of the 2008 International Conference on Compilers, 2008
2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007
2006
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006
2005
Design and analysis of an NoC architecture from performance, reliability and energy perspective.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005