Christos Vezyrtzis

According to our database1, Christos Vezyrtzis authored at least 22 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Efficient AI System Design With Cross-Layer Approximate Computing.
Proc. IEEE, 2020

2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

IBM z14 design methodology enhancements in the 14-nm technology node.
IBM J. Res. Dev., 2018


Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


Effect of HCI degradation on the variability of MOSFETS.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

26.2 Power supply noise in a 22nm z13™ microprocessor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017


2016
A statistical critical path monitor in 14nm CMOS.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Resonant clock mega-mesh for the IBM z13<sup>TM</sup>.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate.
IEEE J. Solid State Circuits, 2014

2013
Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques.
PhD thesis, 2013

A flexible, clockless digital filter.
Proceedings of the ESSCIRC 2013, 2013

2012
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Direct processing of mpeg audio using companding and BFP techniques.
Proceedings of the IEEE International Conference on Acoustics, 2011

2009
Processing of Signals using Level-crossing Sampling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Voltage references for ultra-low supply voltages.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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