Christopher W. Fletcher

Orcid: 0000-0002-9995-5995

Affiliations:
  • University of Illinois Urbana-Champaign, IL, USA


According to our database1, Christopher W. Fletcher authored at least 100 papers between 2010 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
RTL2MμPATH: Multi-μPATH Synthesis with Applications to Hardware Security Verification.
CoRR, 2024

FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design.
CoRR, 2024

Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud (Extended Version).
CoRR, 2024

GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers.
Proceedings of the 33rd USENIX Security Symposium, 2024

GPU.zip: On the Side-Channel Implications of Hardware-Based Graphical Data Compression.
Proceedings of the IEEE Symposium on Security and Privacy, 2024

ConjunCT: Learning Inductive Invariants to Prove Unbounded Instruction Safety Against Microarchitectural Timing Attacks.
Proceedings of the IEEE Symposium on Security and Privacy, 2024

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract).
Proceedings of the 2024 ACM Workshop on Highlights of Parallel Computing, 2024

Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

Everywhere All at Once: Co-Location Attacks on Public Cloud FaaS.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86.
IEEE Micro, 2023

MAD: Microarchitectural Attacks and Defenses (Dagstuhl Seminar 23481).
Dagstuhl Reports, 2023

DECLASSIFLOW: A Static Analysis for Modeling Non-Speculative Knowledge to Relax Speculative Execution Security Measures (Full Version).
CoRR, 2023

Synchronization Storage Channels (S2C): Timer-less Cache Side-Channel Attacks on the Apple M1 via Hardware Synchronization Instructions.
Proceedings of the 32nd USENIX Security Symposium, 2023

DVFS Frequently Leaks Secrets: Hertzbleed Attacks Beyond SIKE, Cryptography, and CPU-Only Data.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

All Your PC Are Belong to Us: Exploiting Non-control-Transfer Instruction BTB Updates for Dynamic PC Extraction.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract).
Proceedings of the 2023 ACM Workshop on Highlights of Parallel Computing, 2023

Declassiflow: A Static Analysis for Modeling Non-Speculative Knowledge to Relax Speculative Execution Security Measures.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker.
Proceedings of the 31st USENIX Security Symposium, 2022

Augury: Using Data Memory-Dependent Prefetchers to Leak Data at Rest.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022

Pagoda: Towards Binary Code Privacy Protection with SGX-based Execute-Only Memory.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

SynthCT: Towards Portable Constant-Time Code.
Proceedings of the 29th Annual Network and Distributed System Security Symposium, 2022

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Leaking Secrets Through Compressed Caches.
IEEE Micro, 2021

Safer Illinois and RokWall: Privacy Preserving University Health Apps for COVID-19.
CoRR, 2021

Speculative taint tracking (STT): a comprehensive protection for speculatively accessed data.
Commun. ACM, 2021

Double-Cross Attacks: Subverting Active Learning Systems.
Proceedings of the 30th USENIX Security Symposium, 2021

Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical.
Proceedings of the 30th USENIX Security Symposium, 2021

DOVE: A Data-Oblivious Virtual Environment.
Proceedings of the 28th Annual Network and Distributed System Security Symposium, 2021

Speculative Privacy Tracking (SPT): Leaking Information From Speculative Execution Without Compromising Privacy.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Optimizing Selective Protection for CNN Resilience.
Proceedings of the 32nd IEEE International Symposium on Software Reliability Engineering, 2021

Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Mind mappings: enabling efficient algorithm-accelerator mapping space search.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Speculative interference attacks: breaking invisible speculation schemes.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Jamais vu: thwarting microarchitectural replay attacks.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
A Retrospective on Path ORAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Creating Foundations for Secure Microarchitectures With Data-Oblivious ISA Extensions.
IEEE Micro, 2020

MicroScope: Enabling Microarchitectural Replay Attacks.
IEEE Micro, 2020

HarDNN: Feature Map Vulnerability Evaluation in CNNs.
CoRR, 2020

Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures.
Proceedings of the 29th USENIX Security Symposium, 2020

Scalable validation of binary lifters.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

Custos: Practical Tamper-Evident Auditing of Operating Systems Using Trusted Execution.
Proceedings of the 27th Annual Network and Distributed System Security Symposium, 2020

Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

PyTorchFI: A Runtime Perturbation Tool for DNNs.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2020

Game of Threads: Enabling Asynchronous Poisoning Attacks.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

Safecracker: Leaking Secrets through Compressed Caches.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Design and Implementation of the Ascend Secure Processor.
IEEE Trans. Dependable Secur. Comput., 2019

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors.
CoRR, 2019

Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World.
Proceedings of the 2019 IEEE Symposium on Security and Privacy, 2019

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum).
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

ExTensor: An Accelerator for Sparse Tensor Algebra.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SecDir: a secure directory to defeat directory side-channel attacks.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

gem5-Approxilyzer: An Open-Source Tool for Application-Level Soft Error Analysis.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Minotaur: Adapting Software Testing Techniques for Hardware Errors.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Path ORAM: An Extremely Simple Oblivious RAM Protocol.
J. ACM, 2018

Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing.
IACR Cryptol. ePrint Arch., 2018

InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Morph: Flexible Acceleration for 3D CNN-Based Video Understanding.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
ZeroTrace : Oblivious Memory Primitives from Intel SGX.
IACR Cryptol. ePrint Arch., 2017

Asymptotically Tight Bounds for Composing ORAM with PIR.
Proceedings of the Public-Key Cryptography - PKC 2017, 2017

HOP: Hardware makes Obfuscation Practical.
Proceedings of the 24th Annual Network and Distributed System Security Symposium, 2017

2016
Oblivious RAM: from theory to practice.
PhD thesis, 2016

Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM.
Proceedings of the Theory of Cryptography - 13th International Conference, 2016

2015
Bucket ORAM: Single Online Roundtrip, Constant Bandwidth Oblivious RAM.
IACR Cryptol. ePrint Arch., 2015

Onion ORAM: A Constant Bandwidth and Constant Client Storage ORAM (without FHE or SWHE).
IACR Cryptol. ePrint Arch., 2015

Constants Count: Practical Improvements to Oblivious RAM.
Proceedings of the 24th USENIX Security Symposium, 2015

PrORAM: dynamic prefetcher for oblivious RAM.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A Low-Latency, Low-Area Hardware Oblivious RAM Controller.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Enhancing Oblivious RAM Performance Using Dynamic Prefetching.
IACR Cryptol. ePrint Arch., 2014

Unified Oblivious-RAM: Improving Recursive ORAM with Locality and Pseudorandomness.
IACR Cryptol. ePrint Arch., 2014

Ring ORAM: Closing the Gap Between Small and Large Client Storage Oblivious RAM.
IACR Cryptol. ePrint Arch., 2014

RAW Path ORAM: A Low-Latency, Low-Area Hardware ORAM Controller with Integrity Verification.
IACR Cryptol. ePrint Arch., 2014

Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Path ORAM: An Extremely Simple Oblivious RAM Protocol.
IACR Cryptol. ePrint Arch., 2013

Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors.
IACR Cryptol. ePrint Arch., 2013

A framework to accelerate sequential programs on homogeneous multicores.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Integrity verification for path Oblivious-RAM.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

Generalized external interaction with tamper-resistant hardware with bounded information leakage.
Proceedings of the CCSW'13, 2013

2012
HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Exploring Many-Core Design Templates for FPGAs and ASICs.
Int. J. Reconfigurable Comput., 2012

Compilation Techniques for Efficient Encrypted Computation.
IACR Cryptol. ePrint Arch., 2012

Towards an interpreter for efficient encrypted computation.
Proceedings of the 2012 ACM Workshop on Cloud computing security, 2012

A low-overhead dynamic optimization framework for multicores.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Brief announcement: distributed shared memory based on computation migration.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Scalable, accurate multicore simulation in the 1000-core era.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Bridging the GPGPU-FPGA efficiency gap.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
MARC: A Many-Core Approach to Reconfigurable Computing.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

<i>ParaLearn</i>: a massively parallel, scalable system for learning interaction networks on FPGAs.
Proceedings of the 24th International Conference on Supercomputing, 2010


  Loading...