Christopher T. Clarke

Robert J. Watson

ACM Trans. Reconfigurable Technol. Syst., 2020

2019

Efficient digital implementation of a multi-precision square-root algorithm.

[BibT_eX]

[DOI]

Alexander E. Beasley

Robert J. Watson

IET Comput. Digit. Tech., 2019

2018

Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.

[BibT_eX]

[DOI]

Siew-Kei Lam

IEEE Trans. Very Large Scale Integr. Syst., 2018

2014

Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

Rapid evaluation of custom instruction selection approaches with FPGA estimation.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Improved Signal Processing Methods for Velocity Selective Neural Recording Using Multi-Electrode Cuffs.

[BibT_eX]

[DOI]

Assad I. Al-Shueli

Nick Donaldson

John Taylor

IEEE Trans. Biomed. Circuits Syst., 2014

2013

FPGA-aware techniques for rapid generation of profitable custom instructions.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Modelling communication overhead for accessing local memories in hardware accelerators.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Examination of the concept of a row-column separated median filter.

[BibT_eX]

[DOI]

Di Wang

A. N. Evans

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Custom instructions with local memory elements without expensive DMA transfers.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Instruction set customization for area-constrained FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2009

Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2009

2008

Analogue/digital interface and communications aspects in a multi-channel ENG recording asic.

[BibT_eX]

[DOI]

John Taylor

Xianhong Xu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Real Time Tracking of Camera Motion Through Cylindrical Passages.

[BibT_eX]

[DOI]

Suchitra Sathyanarayana

Srikanthan Thambipillai

Proceedings of the 15th International Conference on Digital Signal Processing, 2007

2006

Rapid generation of custom instructions using predefined dataflow structures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Profile Directed Instruction Cache Tuning for Embedded Systems.

[BibT_eX]

[DOI]

Kugan Vivekanandarajah

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

2005

Elimination of sign precomputation in flat CORDIC.

[BibT_eX]

[DOI]

Suchitra Sathyanarayana

S. Sukthankar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design.

[BibT_eX]

Kugan Vivekanandarajah

Saurav Bhattacharyya

Proceedings of the International Conference on Embedded Systems and Applications, 2003

1999

VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv.

[BibT_eX]

[DOI]

Manish Bhardwaj

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

A Reverse Converter for the 4-moduli Superset {2n-1, 2n, 2n+1, 2n+1+1}.

[BibT_eX]

[DOI]

Manish Bhardwaj

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998

Designing efficient residue arithmetic based VLSI correlators.

[BibT_eX]

[DOI]

Aniruddha A. Deodhar

Manish Bhardwaj