Christopher M. Ward

Orcid: 0000-0003-0227-0189

According to our database1, Christopher M. Ward authored at least 8 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
ngsReports: a Bioconductor package for managing FastQC reports and other NGS related log files.
Bioinform., 2020

2015
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.
IEEE J. Solid State Circuits, 2011

An 800MS/s dual-residue pipeline ADC in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2004
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm<sup>2</sup> 0.13-μm CMOS.
IEEE J. Solid State Circuits, 2004

1999
A single-chip universal digital satellite receiver with 480-MHz IF input.
IEEE J. Solid State Circuits, 1999


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