Christopher Blochwitz

According to our database1, Christopher Blochwitz authored at least 20 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
RemEduLa - Remote Education Laboratory for FPGA Design Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A comparative survey of open-source application-class RISC-V processor implementations.
Proceedings of the CF '21: Computing Frontiers Conference, 2021

StreamGrid - An AXI-Stream-Compliant Overlay Architecture.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Hardware-aided update acceleration in a hybrid Semantic Web database system.
J. Supercomput., 2020

2018
Hardware-Accelerated Index Construction for Semantic Web.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs.
Microprocess. Microsystems, 2017

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Continuous live-tracing as debugging approach on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
Runtime Adaptive Hybrid Query Engine based on FPGAs.
Open J. Databases, 2016

Constructing Large-Scale Semantic Web Indices for the Six RDF Collation Orders.
Open J. Big Data, 2016

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Hardware-accelerated pose estimation for embedded systems using Vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Adaptive allocation of default router paths in Network-on-Chips for latency reduction.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015
PatTrieSort - External String Sorting based on Patricia Tries.
Open J. Databases, 2015

Automated composition and execution of hardware-accelerated operator graphs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Hybrid FPGA approach for a B<sup>+</sup> tree in a Semantic Web database system.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An architectural template for composing application specific datapaths at runtime.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs.
Proceedings of the Nordic Circuits and Systems Conference, 2015


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