Christopher Batten
Orcid: 0000-0002-2835-667XAffiliations:
- Cornell University, Ithaca, NY, USA
According to our database1,
Christopher Batten
authored at least 57 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks.
CoRR, 2024
Accelerating Seed Location Filtering in DNA Read Mapping Using a Commercial Compute-in-SRAM Architecture.
CoRR, 2024
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator.
IEEE Comput. Archit. Lett., 2024
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
2023
IEEE Micro, 2023
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report.
CoRR, 2023
GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023
Formal Verification of the Stall Invariant Property for Latency-Insensitive RTL Modules.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
CIFER: A 12nm, 16mm<sup>2</sup>, 22-Core SoC with a 1541 LUT6/mm<sup>2</sup> 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
2021
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies.
IEEE Des. Test, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification.
IEEE Micro, 2020
Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
2016
JIT-assisted fast-forward embedding and instrumentation to enable fast, accurate, and agile simulation.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
2013
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators.
ACM Trans. Comput. Syst., 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
2011
Proceedings of the NOCS 2011, 2011
Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011
2010
Simplified vector-thread architectures for flexible and efficient data-parallel accelerators.
PhD thesis, 2010
Re-architecting DRAM memory systems with monolithically integrated silicon photonics.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
2009
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.
IEEE Micro, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
2004
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004