Christopher A. Healy

Affiliations:
  • Furman University, Greenville, SC, USA


According to our database1, Christopher A. Healy authored at least 24 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Have Films Become More Visually Intense?
Proceedings of the 2019 ACM Southeast Conference, 2019

2018
StreetTraffic: a library for traffic flow data collection and analysis.
Proceedings of the ACMSE 2018 Conference, Richmond, KY, USA, March 29-31, 2018, 2018

2017
Computer Science Topics in First- and Second- Year Seminar Courses.
Proceedings of the 2017 ACM SIGCSE Technical Symposium on Computer Science Education, 2017

2010
Parametric timing analysis and its application to dynamic voltage scaling.
ACM Trans. Embed. Comput. Syst., 2010

2009
Extending the Path Analysis Technique to Obtain a Soft WCET.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

2007
Generalizing parametric timing analysis.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

2006
Improving WCET by applying worst-case path optimizations.
Real Time Syst., 2006

2005
Improving WCET by applying a WC code-positioning optimization.
ACM Trans. Archit. Code Optim., 2005

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling.
Proceedings of the 26th IEEE Real-Time Systems Symposium (RTSS 2005), 2005

Improving WCET by Optimizing Worst-Case Paths.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

2004
WCET Code Positioning.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

Tuning the WCET of Embedded Applications.
Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

2002
Automatic Detection and Exploitation of Branch Constraints for Timing Analysis.
IEEE Trans. Software Eng., 2002

2001
Parametric Timing Analysis.
Proceedings of the 2001 ACM SIGPLAN Workshop on Optimization of Middleware and Distributed Systems, 2001

2000
Supporting Timing Analysis by Automatic Bounding of Loop Iterations.
Real Time Syst., 2000

1999
Bounding Pipeline and Instruction Cache Performance.
IEEE Trans. Computers, 1999

Timing Constraint Specification and Analysis.
Softw. Pract. Exp., 1999

Timing Analysis for Data and Wrap-Around Fill Caches.
Real Time Syst., 1999

Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints.
Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium, 1999

1998
Bounding Loop Iterations for Timing Analysis.
Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium, 1998

1997
Timing Analysis for Data Caches and Set-Associative Caches.
Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium, 1997

1996
Supporting the specification and analysis of timing constraints.
Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium, 1996

1995
Integrating the Timing Analysis of Pipelining and Instruction Caching.
Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995


  Loading...