Christophe Wolinski
According to our database1,
Christophe Wolinski
authored at least 43 papers
between 1998 and 2013.
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Bibliography
2013
Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013
2012
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation.
ACM Trans. Reconfigurable Technol. Syst., 2012
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture.
Int. J. Embed. Real Time Commun. Syst., 2012
2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Combined scheduling and instruction selection for processors with reconfigurable cell fabric.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010
2009
Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel.
ACM Trans. Design Autom. Electr. Syst., 2009
Constraint-Driven Identification of Application Specific Instructions in the <i>DURASE</i> System.
Proceedings of the Embedded Computer Systems: Architectures, 2009
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications.
Proceedings of the Design, Automation and Test in Europe, 2009
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
2008
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
Proceedings of the FPL 2008, 2008
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
A New High Performance Multi Gigabit String Matching Engine.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
2004
A constraints programming approach to communication scheduling on SoPC architectures.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
2003
J. Syst. Archit., 2003
Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming.
J. Syst. Archit., 2003
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003
A Preliminary Study of Molecular Dynamics on Reconfigurable Computers.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
2001
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system.
J. Syst. Archit., 2001
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
2000
Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System.
Proceedings of the 13th International Symposium on System Synthesis, 2000
Efficient Scheduling of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs in the CODESIS System.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998