Christophe Jégo

Orcid: 0000-0001-5964-6277

According to our database1, Christophe Jégo authored at least 120 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers.
CoRR, 2024

2023
High-performance hard-input LDPC decoding on multi-core devices for optical space links.
J. Syst. Archit., April, 2023

A DSEL for high throughput and low latency software-defined radio on multicore CPUs.
Concurr. Comput. Pract. Exp., 2023

Low-Complexity Algorithm for the Minimum Distance Properties of PAC Codes.
Proceedings of the 12th International Symposium on Topics in Coding, 2023

AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoC.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Model Based Design of FMCW Radar Processing Systems on FPGA Platforms.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
A novel JFG detection-decoding approach of a vertical shuffle scheduling for iterative MIMO receivers with NB-LDPC codes.
Signal Process., 2022

Methodology to Adapt Neural Network on Constrained Device at Topology level.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

An IoT SoC for Agricultural Applications.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

High-throughput FFT architectures using HLS tools.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices.
Proceedings of the Design and Architecture for Signal and Image Processing, 2022

2021
How to Feed a Growing Population - An IoT Approach to Crop Health and Growth.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

An Energy Efficient and Scalable Node Architecture for Sensor Network.
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Tailored List Decoding of Polar Codes.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

2020
High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors.
J. Signal Process. Syst., 2020

Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices.
J. Signal Process. Syst., 2020

Model-based Design of Hardware SC Polar Decoders for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2020

Low-latency and high-throughput software turbo decoders on multi-core architectures.
Ann. des Télécommunications, 2020

Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

High speed LDPC decoding for optical space link.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Fair comparison of hardware and software LDPC decoder implementations for SDR space links.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Fast and Flexible Software Polar List Decoders.
J. Signal Process. Syst., 2019

AFF3CT: A Fast Forward Error Correction Toolbox!
SoftwareX, 2019

Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Precision Agriculture for Small to Medium Size Farmers - An IoT Approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding.
J. Signal Process. Syst., 2018

High-performance software implementations of SCAN decoder for polar codes.
Ann. des Télécommunications, 2018

Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

ADMM hardware decoder for regular LDPC codes using a NISC-based architecture.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference, 2018

MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard.
Proceedings of the 4th Workshop on Programming Models for SIMD/Vector Processing, 2018

High data rate and flexible hardware QC-LDPC decoder for satellite optical communications.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Transport Triggered Polar Decoders.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Model-based Design of Efficient LDPC Decoder Architectures.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Custom Low Power Processor for Polar Decoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hardware design of Euclidean Projection modules for ADMM LDPC decoding.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

From multicore LDPC decoder implementations to FPGA decoder architectures: a case study.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes.
J. Signal Process. Syst., 2017

Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes.
Proceedings of the 25th International Conference on Software, 2017

Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Successive cancellation decoder for very long polar codes.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Low-latency software LDPC decoders for x86 multi-core devices.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Improving performance of SCMA MPA decoders using estimation of conditional probabilities.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures.
Proceedings of the 2017 IEEE Symposium on Computers and Communications, 2017

An LP-based algorithm for decoding terminated LDPC convolutional codes.
Proceedings of the International Conference on Internet of Things, 2017

2016
Lowering the Error Floor of Turbo Codes With CRC Verification.
IEEE Wirel. Commun. Lett., 2016

Real Time LP Decoding of LDPC Codes for High Correction Performance Applications.
IEEE Wirel. Commun. Lett., 2016

High-Throughput Multi-Core LDPC Decoders Based on x86 Processor.
IEEE Trans. Parallel Distributed Syst., 2016

Low-Complexity Soft Detection of QAM Demapper for a MIMO System.
IEEE Commun. Lett., 2016

Fast Converging ADMM-Penalized Algorithm for LDPC Decoding.
IEEE Commun. Lett., 2016

Evaluation of the hardware complexity of the ADMM approach for LDPC decoding.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2016

Lowering the error floor of double-binary turbo codes: The flip and check algorithm.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Comparison of different schedulings for the ADMM based LDPC decoding.
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

A scalable 3-phase polar decoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Memory reduction techniques for successive cancellation decoding of polar codes.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Multicore implementation of LDPC decoders based on ADMM algorithm.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Hardware architecture for lowering the error floor of LTE turbo codes.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Multi-Gb/s Software Decoding of Polar Codes.
IEEE Trans. Signal Process., 2015

High-Throughput LDPC Decoder on Low-Power Embedded Processors.
IEEE Commun. Lett., 2015

Partial sums computation in polar codes decoding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Hardware implementation of a soft cancellation decoder for polar codes.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014
A Flexible NISC-Based LDPC Decoder.
IEEE Trans. Signal Process., 2014

GPU-like on-chip system for decoding LDPC codes.
ACM Trans. Embed. Comput. Syst., 2014

A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices.
IEEE Embed. Syst. Lett., 2014

Symbol-based BP detection for MIMO systems associated with non-binary LDPC codes.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

Software polar decoder on an embedded processor.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Low-complexity LDPC-coded iterative MIMO receiver based on belief propagation algorithm for detection.
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

Low-complexity layered BP-based detection and decoding for a NB-LDPC coded MIMO system.
Proceedings of the IEEE International Conference on Communications, 2014

2013
Méthodologie d'optimisation des processeurs embarqués. Une approche favorisant la réduction de la surface et de la consommation des processeurs embarqués.
Tech. Sci. Informatiques, 2013

Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders.
IEEE Commun. Lett., 2013

Softcore Processor Optimization According to Real-Application Requirements.
IEEE Embed. Syst. Lett., 2013

Partial sums generation architecture for successive cancellation decoding of polar codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Muller C-element based Decoder (MCD): A decoder against transient faults.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes.
IEEE Trans. Signal Process., 2012

A contribution to the reduction of the dynamic power dissipation in the turbo decoder.
Ann. des Télécommunications, 2012

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A space-time redundancy technique for embedded stochastic error correction.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

An LDPC decoding method for fault-tolerant digital logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.
J. Signal Process. Syst., 2011

Stochastic Multiple Stream Decoding of Cortex Codes.
IEEE Trans. Signal Process., 2011

Hardware efficiency versus error probability in unreliable computation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard.
Proceedings of the IEEE International Conference on Acoustics, 2011

Assertion support in high-level synthesis design flow.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

2010
Stochastic Decoding of Turbo Codes.
IEEE Trans. Signal Process., 2010

Design and implementation of a soft-decision decoder for Cortex codes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A new single-error correction scheme based on self-diagnosis residue number arithmetic.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
J. Signal Process. Syst., 2009

Turbo decoding of product codes using adaptive belief propagation.
IEEE Trans. Commun., 2009

Design of rotated QAM mapper/demapper for the DVB-T2 standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Design of an Iterative Receiver for Linearly Precoded MIMO Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Blind Frame Synchronization of Product Codes Based on the Adaptation of the Parity Check Matrix.
Proceedings of IEEE International Conference on Communications, 2009

FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices.
IEEE Trans. Signal Process., 2008

Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design.
EURASIP J. Wirel. Commun. Netw., 2008

A highly parallel Turbo Product Code decoder without interleaving resource.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

On the higher efficiency of parallel Reed-Solomon turbo-decoding.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s.
Ann. des Télécommunications, 2007

Energy Efficient Turbo Decoder with Reduced State Metric Quantization.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Turbo Decoding of Product Codes based on the Modified Adaptive Belief Propagation Algorithm.
Proceedings of the IEEE International Symposium on Information Theory, 2007

Towards Gb/s turbo decoding of product code onto an FPGA device.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Efficient architecture for Reed Solomon block turbo code.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

Reduced Complexity Iterative Multi-User Detector for IDMA (Interleave-Division Multiple Access) System.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
C-based rapid prototyping for digital signal processing.
Proceedings of the 13th European Signal Processing Conference, 2005

Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Hardware Virtual Components Compliant with Communication System Standards.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Synthèse architecturale d'applications temps réel pour technologies submicroniques.
Tech. Sci. Informatiques, 2004

Reed-Solomon behavioral virtual component for communication systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001
Architectural synthesis of digital signal processing applications dedicated to submicron technologies.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
Architectural Synthesis with Interconnection Cost Control.
Proceedings of the VLSI: Systems on a Chip, 1999


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