Christophe Jégo

Tech. Sci. Informatiques, 2013

Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders.

[BibT_eX]

[DOI]

Oscar Sanchez

Michel Jézéquel

IEEE Commun. Lett., 2013

Softcore Processor Optimization According to Real-Application Requirements.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

Partial sums generation architecture for successive cancellation decoding of polar codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Muller C-element based Decoder (MCD): A decoder against transient faults.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy.

[BibT_eX]

[DOI]

Paolo Meloni

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes.

[BibT_eX]

[DOI]

Patrick Adde

Daniel Gomez Toro

IEEE Trans. Signal Process., 2012

A contribution to the reduction of the dynamic power dissipation in the turbo decoder.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2012

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A space-time redundancy technique for embedded stochastic error correction.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

An LDPC decoding method for fault-tolerant digital logic.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard.

[BibT_eX]

[DOI]

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011

Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Stochastic Multiple Stream Decoding of Cortex Codes.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2011

Hardware efficiency versus error probability in unreliable computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2011

Assertion support in high-level synthesis design flow.

[BibT_eX]

[DOI]

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

2010

Stochastic Decoding of Turbo Codes.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2010

Design and implementation of a soft-decision decoder for Cortex codes.

[BibT_eX]

[DOI]

Patrick Adde

Jorge Ernesto Pérez Chamorro

Raphaël Le Bidan

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A new single-error correction scheme based on self-diagnosis residue number arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Turbo decoding of product codes using adaptive belief propagation.

[BibT_eX]

[DOI]

Warren J. Gross

IEEE Trans. Commun., 2009

Design of rotated QAM mapper/demapper for the DVB-T2 standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Design of an Iterative Receiver for Linearly Precoded MIMO Systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Blind Frame Synchronization of Product Codes Based on the Adaptation of the Parity Check Matrix.

[BibT_eX]

[DOI]

Rodrigue Imad

Sébastien Houcke

Proceedings of IEEE International Conference on Communications, 2009

FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems.

[BibT_eX]

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008

Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices.

[BibT_eX]

[DOI]

Saeed Sharifi Tehrani

Bo Zhu

Warren J. Gross

IEEE Trans. Signal Process., 2008

Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design.

[BibT_eX]

[DOI]

EURASIP J. Wirel. Commun. Netw., 2008

A highly parallel Turbo Product Code decoder without interleaving resource.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

On the higher efficiency of parallel Reed-Solomon turbo-decoding.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s.

[BibT_eX]

[DOI]

Patrick Adde

Camille Leroux

Ann. des Télécommunications, 2007

Energy Efficient Turbo Decoder with Reduced State Metric Quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Turbo Decoding of Product Codes based on the Modified Adaptive Belief Propagation Algorithm.

[BibT_eX]

[DOI]

Warren J. Gross

Proceedings of the IEEE International Symposium on Information Theory, 2007

Towards Gb/s turbo decoding of product code onto an FPGA device.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.

[BibT_eX]

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Efficient architecture for Reed Solomon block turbo code.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006

Reduced Complexity Iterative Multi-User Detector for IDMA (Interleave-Division Multiple Access) System.

[BibT_eX]

[DOI]

Irene Masinjara Mahafeno

Charlotte Langlais

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005

C-based rapid prototyping for digital signal processing.

[BibT_eX]

[DOI]

Proceedings of the 13th European Signal Processing Conference, 2005

Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.

[BibT_eX]

Caaliph Andriamisaina

Catherine Dezan

Bernard Pottier

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Hardware Virtual Components Compliant with Communication System Standards.

[BibT_eX]

[DOI]

Nabil Abdelli

Pierre Bomel

Anne-Marie Fouilliart

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Synthèse architecturale d'applications temps réel pour technologies submicroniques.

[BibT_eX]

[DOI]

Eric Martin

Tech. Sci. Informatiques, 2004

Reed-Solomon behavioral virtual component for communication systems.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001

Architectural synthesis of digital signal processing applications dedicated to submicron technologies.

[BibT_eX]

[DOI]

Eric Martin

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999

Architectural Synthesis with Interconnection Cost Control.

[BibT_eX]