Christophe Dubach

Orcid: 0000-0003-4811-2469

Affiliations:
  • McGill University, Canada
  • University of Edinburgh, UK (former)


According to our database1, Christophe Dubach authored at least 64 papers between 2005 and 2024.

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Bibliography

2024
Efficient Assignment with Time Constraints for Heterogeneous DSP Systems.
Proceedings of the IEEE Workshop on Signal Processing Systemsm, 2024

Latent Idiom Recognition for a Minimalist Functional Array Language Using Equality Saturation.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs.
ACM Trans. Embed. Comput. Syst., October, 2023

LAGrad: Statically Optimized Differentiable Programming in MLIR.
Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

2022
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators.
ACM Trans. Archit. Code Optim., 2022

GPU acceleration of finite state machine input execution: Improving scale and performance.
Softw. Test. Verification Reliab., 2022

From functional to imperative: combining destination-passing style and views.
Proceedings of the ARRAY '22: 8th ACM SIGPLAN International Workshop on Libraries, 2022

Optimizing data reshaping operations in functional IRs for high-level synthesis.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022

Generating Work Efficient Scan Implementations for GPUs the Functional Way.
Proceedings of the Euro-Par 2022: Parallel Processing, 2022

Mapping parallelism in a functional IR through constraint satisfaction: a case study on convolution for mobile GPUs.
Proceedings of the CC '22: 31st ACM SIGPLAN International Conference on Compiler Construction, Seoul, South Korea, April 2, 2022

2021
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Code Generation for Room Acoustics Simulations with Complex Boundary Conditions.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Generating high performance code for irregular data structures using dependent types.
Proceedings of the FHPNC 2021: Proceedings of the 9th ACM SIGPLAN International Workshop on Functional High-Performance and Numerical Computing, 2021

Fast Optimisation of Convolutional Neural Network Inference using System Performance Models.
Proceedings of the EuroMLSys@EuroSys 2021, 2021

2020
Tiling Optimizations for Stencil Computations Using Rewrite Rules in Lift.
ACM Trans. Archit. Code Optim., 2020

Optimising the Performance of Convolutional Neural Networks across Computing Systems using Transfer Learning.
CoRR, 2020

Binary Ostensibly-Implicit Trees for Fast Collision Detection.
Comput. Graph. Forum, 2020

High-level hardware feature extraction for GPU performance prediction of stencils.
Proceedings of the GPGPU@PPoPP '20: 13th Annual Workshop on General Purpose Processing using Graphics Processing Unit colocated with 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020

Automatic generation of specialized direct convolutions for mobile GPUs.
Proceedings of the GPGPU@PPoPP '20: 13th Annual Workshop on General Purpose Processing using Graphics Processing Unit colocated with 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020

DelayRepay: delayed execution for kernel fusion in Python.
Proceedings of the DLS 2020: Proceedings of the 16th ACM SIGPLAN International Symposium on Dynamic Languages, 2020

Generating fast sparse matrix vector multiplication from a high level generic functional IR.
Proceedings of the CC '20: 29th International Conference on Compiler Construction, 2020

2019
High-level synthesis of functional patterns with Lift.
Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, 2019

Position-dependent arrays and their application for high performance code generation.
Proceedings of the 8th ACM SIGPLAN International Workshop on Functional High-Performance and Numerical Computing, 2019

2018
Bulk-synchronous parallel simultaneous BVH traversal for collision detection on GPUs.
Proceedings of the ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games, 2018

Generating High Performance GPU Code using Rewrite Rules with Lift.
Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

High performance stencil code generation with lift.
Proceedings of the 2018 International Symposium on Code Generation and Optimization, 2018

Automatic Matching of Legacy Code to Heterogeneous APIs: An Idiomatic Approach.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Accelerated Finite State Machine Test Execution Using GPUs.
Proceedings of the 25th Asia-Pacific Software Engineering Conference, 2018

2017
A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor.
ACM Trans. Embed. Comput. Syst., 2017

Strategy Preserving Compilation for Parallel Functional Code.
CoRR, 2017

Just-In-Time GPU Compilation for Interpreted Languages with Partial Evaluation.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

ParTeCL: parallel testing using OpenCL.
Proceedings of the 26th ACM SIGSOFT International Symposium on Software Testing and Analysis, Santa Barbara, CA, USA, July 10, 2017

Compiler-assisted test acceleration on GPUs for embedded software.
Proceedings of the 26th ACM SIGSOFT International Symposium on Software Testing and Analysis, Santa Barbara, CA, USA, July 10, 2017

Lift: a functional data-parallel IR for high-performance GPU code generation.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

2016
Selecting Heterogeneous Cores for Diversity.
ACM Trans. Archit. Code Optim., 2016

Four Metrics to Evaluate Heterogeneous Multicores.
ACM Trans. Archit. Code Optim., 2016

Diversity: A Design Goal for Heterogeneous Processors.
IEEE Comput. Archit. Lett., 2016

Performance portable GPU code generation for matrix multiplication.
Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit, 2016

A machine learning approach to mapping streaming workloads to dynamic multicore processors.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

Matrix multiplication beyond auto-tuning: rewrite-based GPU code generation.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
Patterns and Rewrite Rules for Systematic Code Generation (From High-Level Functional Patterns to High-Performance OpenCL Code).
CoRR, 2015

Runtime Code Generation and Data Management for Heterogeneous Computing in Java.
Proceedings of the Principles and Practices of Programming on The Java Platform, 2015

Carpet unrolling for character control on uneven terrain.
Proceedings of the 8th ACM SIGGRAPH Conference on Motion in Games, 2015

Generating performance portable code using rewrite rules: from high-level functional expressions to high-performance OpenCL code.
Proceedings of the 20th ACM SIGPLAN International Conference on Functional Programming, 2015

2014
Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems 2015 (ADAPT'15).
CoRR, 2014

Community-driven reviewing and validation of publications.
Proceedings of the 1st ACM SIGPLAN Workshop on Reproducible Research Methodologies and New Publication Models in Computer Engineering, 2014

A Composable Array Function Interface for Heterogeneous Computing in Java.
Proceedings of the ARRAY'14: Proceedings of the 2014 ACM SIGPLAN International Workshop on Libraries, 2014

Exploiting GPU Hardware Saturation for Fast Compiler Optimization.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Measuring flexibility in single-ISA heterogeneous processors.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

Automatic optimization of thread-coarsening for graphics processors.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Dynamic microarchitectural adaptation using machine learning.
ACM Trans. Archit. Code Optim., 2013

A large-scale cross-architecture evaluation of thread-coarsening.
Proceedings of the International Conference for High Performance Computing, 2013

2012
Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy.
ACM Trans. Embed. Comput. Syst., 2012

Compiling a high-level language for GPUs: (via language support for architectures and compilers).
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012

2011
An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration.
IEEE Trans. Computers, 2011

2010
A Predictive Model for Dynamic Microarchitectural Adaptivity Control.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
Using machine-learning to efficiently explore the architecture/compiler co-design space.
PhD thesis, 2009

Portable compiler optimisation across embedded programs and microarchitectures using machine learning.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Rapid early-stage microarchitecture design using predictive models.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Exploring and predicting the architecture/optimising compiler co-design space.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Fast compiler optimisation evaluation using code-feature based performance prediction.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Automatic performance model construction for the fast software exploration of new hardware designs.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005


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