Christophe Alias

Orcid: 0000-0002-5387-2369

According to our database1, Christophe Alias authored at least 22 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Lightweight Array Contraction by Trace-Based Polyhedral Analysis.
Proceedings of the High Performance Computing. ISC High Performance 2022 International Workshops - Hamburg, Germany, May 29, 2022

2021
Monoparametric Tiling of Polyhedral Programs.
Int. J. Parallel Program., 2021

Data-aware process networks.
Proceedings of the CC '21: 30th ACM SIGPLAN International Conference on Compiler Construction, 2021

2019
Fkcc: The Farkas Calculator.
Proceedings of the Formal Methods. FM 2019 International Workshops, 2019

Contributions to Program Optimization and High-Level Synthesis. (Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau).
, 2019

2018
Improving Communication Patterns in Polyhedral Process Networks.
CoRR, 2018

2017
Optimizing Affine Control With Semantic Factorizations.
ACM Trans. Archit. Code Optim., 2017

2014
On Program Equivalence with Reductions.
Proceedings of the Static Analysis - 21st International Symposium, 2014

2013
Rank: A Tool to Check Program Termination and Computational Complexity.
Proceedings of the Sixth IEEE International Conference on Software Testing, 2013

2012
FPGA-specific synthesis of loop-nests with pipelined computational cores.
Microprocess. Microsystems, 2012

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA.
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011
Automatic Generation of FPGA-Specific Pipelined Accelerators.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs.
Proceedings of the Static Analysis - 17th International Symposium, 2010

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors.
Proceedings of the PACT 2009, 2009

2007
Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

2006
Region array SSA.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Optimisation de programmes par reconnaissance de templates. (Program Optimization by Template Recognition and Replacement).
PhD thesis, 2005

On Domain-Specific Languages Reengineering.
Proceedings of the Generative Programming and Component Engineering, 2005

Deciding Where to Call Performance Libraries.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2003
On the Recognition of Algorithm Templates.
Proceedings of the Compiler Optimization Meets Compiler Verification, 2003

Algorithm Recognition based on Demand-Driven Data-flow Analysis.
Proceedings of the 10th Working Conference on Reverse Engineering, 2003


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