Christoforos Kachris

Orcid: 0000-0003-0818-1902

Affiliations:
  • University of West Attica, Greece
  • Delft University of Technology, Netherlands (former)


According to our database1, Christoforos Kachris authored at least 79 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Hardware Acceleration of LLMs: A comprehensive survey and comparison.
CoRR, 2024

A Survey on Hardware Accelerators for Large Language Models.
CoRR, 2024

2021
Utilizing cloud FPGAs towards the open neural network standard.
Sustain. Comput. Informatics Syst., 2021

FPGA Acceleration of Generative Adversarial Networks for Image Reconstruction.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Hardware Acceleration of Decision Tree Learning Algorithm.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Automatic Generation of FPGA Kernels From Open Format CNN Models.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Approximate Similarity Search with FAISS Framework Using FPGAs on the Cloud.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

FPGA Acceleration of Approximate KNN Indexing on High- Dimensional Vectors.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Hardware Acceleration on Gaussian Naive Bayes Machine Learning Algorithm.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Modular FPGA Acceleration of Data Analytics in Heterogenous Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
The VINEYARD integrated framework for hardware accelerators in the cloud.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Acceleration of image classification with Caffe framework using FPGA.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

A Novel Framework for the Seamless Integration of FPGA Accelerators with Big Data Analytics Frameworks in Heterogeneous Data Centers.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
An FPGA-based Integrated MapReduce Accelerator Platform.
J. Signal Process. Syst., 2017

Hardware accelerators for financial applications in HDL and High Level Synthesis.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

SPynq: Acceleration of machine learning applications over Spark on Pynq.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Spark acceleration on FPGAs: A use case on machine learning in Pynq.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

High-Performance Hardware Accelerators for Solving Ordinary Differential Equations.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

VineTalk: Simplifying software access and sharing of FPGAs in datacenters.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

FPGA acceleration of spark applications in a Pynq cluster.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Discharging the Network From Its Flow Control Headaches: Packet Drops and HOL Blocking.
IEEE/ACM Trans. Netw., 2016

Modeling Cache Memory Utilization on Multicore Using Common Pool Resource Game on Cellular Automata.
ACM Trans. Model. Comput. Simul., 2016

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations.
CoRR, 2016

A Survey on FEC Codes for 100 G and Beyond Optical Networks.
IEEE Commun. Surv. Tutorials, 2016

Performance and energy evaluation of spark applications on low-power SoCs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A survey on reconfigurable accelerators for cloud computing.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
A MapReduce scratchpad memory for multi-core cloud computing applications.
Microprocess. Microsystems, 2015

Cognitive Optical Network Testbed: EU Project CHRON [Invited].
JOCN, 2015

High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Optical networking solutions and technologies in the big data era.
Proceedings of the 17th International Conference on Transparent Optical Networks, 2015

A roadmap on optical interconnects in data centre networks.
Proceedings of the 17th International Conference on Transparent Optical Networks, 2015

Design of Optical Network Unit (ONU) for hybrid TDM/WDM NG-PON.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Network Function Virtualization based on FPGAs: A Framework for all-Programmable network devices.
CoRR, 2014

Experimental demonstration of a cognitive optical network for reduction of restoration time.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Advanced modulation formats in cognitive optical networks: EU project CHRON demonstration.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Flexible FEC codes for next-generation software-defined optical transceivers.
Proceedings of the 16th International Conference on Transparent Optical Networks, 2014

A configurable mapreduce accelerator for multi-core FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
NP-SARC: Scalable network processing in the SARC multi-core FPGA platform.
J. Syst. Archit., 2013

Optical OFDM-based Data Center Networks.
J. Networks, 2013

Optical interconnection networks in data centers: recent trends and future challenges.
IEEE Commun. Mag., 2013

Power consumption evaluation of all-optical data center networks.
Clust. Comput., 2013

Automatic implementation of low-complexity QC-LDPC encoders.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Optical interconnection networks for data centers.
Proceedings of the 17th International Conference on Optical Networking Design and Modeling, 2013

Optimization of Shared-Memory Multicore Systems Using Game Theory and Genetic Algorithms on Cellular Automata Lattices.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Evaluating conflicts impact over shared last-level cache using public goods game on cellular automata.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A Survey on Optical Interconnects for Data Centers.
IEEE Commun. Surv. Tutorials, 2012

Energy efficient flexible-bandwidth OFDM-based data center network.
Proceedings of the 1st IEEE International Conference on Cloud Networking, 2012

Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications.
Proceedings of the Cloud Computing - Third International Conference, 2012

Energy efficient data center network based on a flexible bandwidth MIMO OFDM optical interconnect.
Proceedings of the 4th IEEE International Conference on Cloud Computing Technology and Science Proceedings, 2012

2011
Transactional memories for multi-processor FPGA platforms.
J. Syst. Archit., 2011

An efficient sequential iterative matching algorithm for CIOQ switches.
Proceedings of the 16th IEEE Symposium on Computers and Communications, 2011

Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Efficient implementation of CIOQ switches with sequential iterative matching algorithms.
Proceedings of the International Conference on Field-Programmable Technology, 2010

End-to-end congestion management for non-blocking multi-stage switching fabrics.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
Design and performance evaluation of an adaptive FPGA for network applications.
Microelectron. J., 2009

2008
ImpBench: A novel benchmark suite for biomedical, microelectronic implants.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

2007
Reconfigurable network processing platforms.
PhD thesis, 2007

A reconfigurable platform for multi-service edge routers.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Design Space Exploration of Configuration Manager for Network Processing Applications.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Configurable Transactional Memory.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
High-performance switching based on buffered crossbar fabrics.
Comput. Networks, 2006

Performance Evaluation of an Adaptive FPGA for Network Applications.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Analysis of a reconfigurable network processor.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Dynamically Reconfigurable Queue Scheduler.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A reconfigurable hardware based embedded scheduler for buffered crossbar switches.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Design of a web switch in a reconfigurable platform.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
An Open TCP/IP Core for Reconfigurable Logic.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Queue Management in Network Processors.
Proceedings of the 2005 Design, 2005

2004
An FPGA-based queue management system for high speed networking devices.
Microprocess. Microsystems, 2004

2003
A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm.
Int. J. Parallel Program., 2003

Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003


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