Christodoulos Peltekis

According to our database, Christodoulos Peltekis authored at least 12 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Floating-Point Multiply-Add with Approximate Normalization for Low-Cost Matrix Engines.

Kosmas Alexandridis, Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos

CoRR, 2024

DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.

Christodoulos Peltekis, Vasileios Titopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

IEEE Comput. Archit. Lett., 2024

A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators.

Dionysios Filippas, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios Ch. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos

IEEE Access, 2024

IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.

Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Error Checking for Sparse Systolic Tensor Arrays.

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

Reusing Softmax Hardware Unit for GELU Computation in Transformers.

Christodoulos Peltekis, Kosmas Alexandridis, Giorgos Dimitrakopoulos

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Exploiting data encoding and reordering for low-power streaming in systolic arrays.

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos

Microprocess. Microsystems, 2023

The Case for Asymmetric Systolic Array Floorplanning.

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos A. Nicopoulos

CoRR, 2023

Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos

Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining.

Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines.

Dionysios Filippas, Christodoulos Peltekis, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.

Christodoulos Peltekis, Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022