Christian Weis
Orcid: 0000-0002-4152-0200
According to our database1,
Christian Weis
authored at least 90 papers
between 2011 and 2024.
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Bibliography
2024
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects.
Proceedings of the IEEE International Test Conference, 2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
The NWRD Dataset: An Open-Source Annotated Segmentation Dataset of Diseased Wheat Crop.
Sensors, August, 2023
A Learning-Based Approach for Single Event Transient Analysis in Pass Transistor Logic.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
J. Signal Process. Syst., 2021
A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Access, 2021
Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems.
Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021
QuantYOLO: A High-Throughput and Power-Efficient Object Detection Network for Resource and Power Constrained UAVs.
Proceedings of the 2021 Digital Image Computing: Techniques and Applications, 2021
Burnt Forest Estimation from Sentinel-2 Imagery of Australia using Unsupervised Deep Learning.
Proceedings of the 2021 Digital Image Computing: Techniques and Applications, 2021
Proceedings of the A Journey of Embedded and Cyber-Physical Systems, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.
J. Signal Process. Syst., 2020
J. Signal Process. Syst., 2020
Proceedings of the RAPIDO 2020 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2020
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.
CoRR, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements.
Proceedings of the XVI International Symposium "Problems of Redundancy in Information and Control Systems", 2019
Proceedings of the International Symposium on Memory Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Des. Test, 2018
Proceedings of the International Symposium on Memory Systems, 2018
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving.
Proceedings of the International Symposium on Memory Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.
J. Signal Process. Syst., 2017
Int. J. Parallel Program., 2017
Int. J. Parallel Program., 2017
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017
Proceedings of the International Symposium on Memory Systems, 2017
Proceedings of the International Symposium on Memory Systems, 2017
An advanced embedded architecture for connected component analysis in industrial applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Microelectron. Reliab., 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
it Inf. Technol., 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Symposium on Memory Systems, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Micro, 2013
TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration.
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2013
Proceedings of the 10th FPGAworld Conference, 2013
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013
Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the International Conference on Computing, Networking and Communications, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the Design, Automation and Test in Europe, 2011