Christian V. Schimpfle

According to our database1, Christian V. Schimpfle authored at least 7 papers between 1997 and 2002.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2002
Minimizing Spurious Switching Activities with Transistor Sizing.
VLSI Design, 2002

2001
Minimizing gate capacitances with transistor sizing.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms.
J. VLSI Signal Process., 1999

Device level based cell modeling for fast power estimation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High-level circuit modeling for power estimation.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1997
Low Power CORDIC Implementation Using Redundant Number Representation.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997


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