Christian Pinto
Orcid: 0000-0001-7060-2742
According to our database1,
Christian Pinto
authored at least 37 papers
between 2010 and 2024.
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Bibliography
2024
CoRR, 2024
One Queue Is All You Need: Resolving Head-of-Line Blocking in Large Language Model Serving.
CoRR, 2024
Zero-Copy, Minimal-Blackout Virtual Machine Migrations Using Disaggregated Shared Memory.
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024
Proceedings of the 2024 ACM Symposium on Cloud Computing, 2024
2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
An Architecture for Heterogeneous High-Performance Computing Systems: Motivation and Requirements.
Proceedings of the IEEE John Vincent Atanasoff International Symposium on Modern Computing, 2023
Adrias: Interference-Aware Memory Orchestration for Disaggregated Cloud Infrastructures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the High Performance Computing - ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24, 2021
Proceedings of the CHEOPS '21: Proceedings of the Workshop on Challenges and Opportunities of Efficient and Performant Storage Systems, 2021
EVOLVE: HPC and cloud enhanced testbed for extracting value from large-scale diverse data.
Proceedings of the CF '21: Computing Frontiers Conference, 2021
A Holistic System Software Integration of Disaggregated Memory for Next-Generation Cloud Infrastructures.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021
Proceedings of the 14th IEEE International Conference on Cloud Computing, 2021
2020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
Exploiting CPU Voltage Margins to Increase the Profit of Cloud Infrastructure Providers.
Proceedings of the 19th IEEE/ACM International Symposium on Cluster, 2019
2018
Hoard: A Distributed Data Caching System to Accelerate Deep Learning Training on the Cloud.
CoRR, 2018
Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2018
2017
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016
On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision.
Proceedings of the European Conference on Networks and Communications, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016
2015
PhD thesis, 2015
IEEE Trans. Parallel Distributed Syst., 2015
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
J. Signal Process. Syst., 2014
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Exploring DMA-assisted prefetching strategies for software caches on multicore clusters.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
SIM<i>in</i>G-1<i>k</i>: A thousand-core simulator running on general-purpose graphical processing units.
Concurr. Comput. Pract. Exp., 2013
VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting.
Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012
2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the 11th IEEE/ACM International Symposium on Cluster, 2011
2010
Scalable instruction set simulator for thousand-core architectures running on GPGPUs.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010