Christian Pilato

Abdul Khader Thalakkattu Moosa

Kanad Basu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Using Static Analysis for Enhancing HLS Security.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., June, 2024

Foundation Models in Augmentative and Alternative Communication: Opportunities and Challenges.

[BibT_eX]

[DOI]

CoRR, 2024

Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction.

[BibT_eX]

[DOI]

Jitendra Bhandari

Pierre-Emmanuel Gaillardon

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Generating Posit-Based Accelerators With High-Level Synthesis.

[BibT_eX]

[DOI]

Raul Murillo

Alberto A. Del Barrio

Guillermo Botella

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., June, 2023

Optimizing the Use of Behavioral Locking for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

A Survey of FPGA Optimization Methods for Data Center Energy Efficiency.

[BibT_eX]

[DOI]

Mattia Tibaldi

IEEE Trans. Sustain. Comput., 2023

CPS Workshop 2023 Proceedings.

[BibT_eX]

[DOI]

Francesca Palumbo

CoRR, 2023

Platform-Aware FPGA System Architecture Generation based on MLIR.

[BibT_eX]

[DOI]

CoRR, 2023

Towards High-Level Synthesis of Quantum Circuits.

[BibT_eX]

[DOI]

Chao Lu

Kanad Basu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

HOLL: Program Synthesis for Higher OrderLogic Locking.

[BibT_eX]

[DOI]

CoRR, 2022

HOLL: Program Synthesis for Higher Order Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2022

Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Composable Design Space Exploration Framework to Optimize Behavioral Locking.

[BibT_eX]

[DOI]

Luca Collini

Abdul Khader Thalakkattu Moosa

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

ALICE: an automatic design flow for eFPGA redaction.

[BibT_eX]

[DOI]

Chiara Muscari Tomajoli

Luca Collini

Jitendra Bhandari

Benjamin Tan

Xifan Tang

Pierre-Emmanuel Gaillardon

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Designing ML-resilient locking at register-transfer level.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

High-level design methods for hardware security: is it the right choice? invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Protecting Hardware IP Cores During High-Level Synthesis.

[BibT_eX]

[DOI]

Behavioral Synthesis for Hardware Security, 2022

2021

ASSURE: RTL Locking Against an Untrusted Foundry.

[BibT_eX]

[DOI]

Animesh Basak Chowdhury

Siddharth Garg

IEEE Trans. Very Large Scale Integr. Syst., 2021

CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

Automatic Generation of Heterogeneous SoC Architectures With Secure Communications.

[BibT_eX]

[DOI]

Mattia Tibaldi

IEEE Embed. Syst. Lett., 2021

A Survey on Domain-Specific Memory Architectures.

[BibT_eX]

[DOI]

CoRR, 2021

On the Optimization of Behavioral Logic Locking for High-Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2021

Compiler Infrastructure for Specializing Domain-Specific Memory Templates.

[BibT_eX]

[DOI]

CoRR, 2021

High-Level Synthesis of Security Properties via Software-Level Abstractions.

[BibT_eX]

[DOI]

Abdul Khader Thalakkattu Moosa

Francesco Regazzoni

CoRR, 2021

Exploring eFPGA-based Redaction for IP Protection.

[BibT_eX]

[DOI]

Jitendra Bhandari

Pierre-Emmanuel Gaillardon

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms.

[BibT_eX]

[DOI]

Dionysios Diamantopoulos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.

[BibT_eX]

[DOI]

Hannah Badier

Jean-Christophe Le Lann

Philippe Coussy

Guy Gogniat

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks.

[BibT_eX]

[DOI]

Nimisha Limaye

Animesh Basak Chowdhury

Mohammed Thari Nabeel

Ozgur Sinanoglu

Siddharth Garg

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications.

[BibT_eX]

[DOI]

Vito Giovanni Castellana

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020

Agile SoC Development with Open ESP.

[BibT_eX]

[DOI]

Davide Giri

CoRR, 2020

Agile SoC Development with Open ESP : Invited Paper.

[BibT_eX]

[DOI]

Davide Giri

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Is Register Transfer Level Locking Secure?

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Black-Hat High-Level Synthesis: Myth or Reality?

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

CAD-Base: An Attack Vector into the Electronics Supply Chain.

[BibT_eX]

[DOI]

Mohammed Thari Nabeel

Krishnendu Chakrabarty

ACM Trans. Design Autom. Electr. Syst., 2019

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

High-Level Synthesis of Benevolent Trojans.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

The Case for Polymorphic Registers in Dataflow Computing.

[BibT_eX]

[DOI]

Catalin Bogdan Ciobanu

Georgi Gaydadjiev

Int. J. Parallel Program., 2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2018

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis.

[BibT_eX]

[DOI]

Pietro Fezzardi

IEEE Des. Test, 2018

TAO: techniques for algorithm-level obfuscation during high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Bridging the Gap Between Software and Hardware Designers Using High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing is Everywhere, 2017

2016

Editorial: Special Issue on Innovative Design Methods for Smart Embedded Systems.

[BibT_eX]

[DOI]

Sara Vinco

ACM Trans. Embed. Comput. Syst., 2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Performance Estimation of Task Graphs Based on Path Profiling.

[BibT_eX]

[DOI]

Marco Lattuada

Int. J. Parallel Program., 2016

Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs.

[BibT_eX]

[DOI]

Gianluca C. Durelli

Fabrizio Spada

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems.

[BibT_eX]

[DOI]

Kenneth L. Shepard

Proceedings of the 53rd Annual Design Automation Conference, 2016

On the design of scalable and reusable accelerators for big data applications.

[BibT_eX]

[DOI]

Qirui Xu

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip.

[BibT_eX]

[DOI]

Emilio G. Cota

Proceedings of the 2016 International Conference on Compilers, 2016

2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

2014

A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE World Forum on Internet of Things, 2014

Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

System-level memory optimization for high-level synthesis of component-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Effective Reconfigurable Design: The FASTER Approach.

[BibT_eX]

[DOI]

Georgi Nedeltchev Gaydadjiev

Tobias Becker

Andreas Brokalakis

Wayne Luk

Ioannis Papaefstathiou

Danilo Pau

Oliver Pell

Dirk Stroobandt

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Antonio Miele

Int. J. Embed. Real Time Commun. Syst., 2013

Dataflow computing with Polymorphic Registers.

[BibT_eX]

[DOI]

Catalin Bogdan Ciobanu

Georgi Gaydadjiev

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.

[BibT_eX]

[DOI]

Riccardo Cattaneo

Marco Domenico Santambrogio

Gianluca Durelli

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A framework for effective exploitation of partial reconfiguration in dataflow computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.

[BibT_eX]

[DOI]

Gianluca Durelli

Alessandro Antonio Nacci

Riccardo Cattaneo

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The FASTER vision for designing dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Dirk Stroobandt

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Bambu: A modular framework for the high level synthesis of memory-intensive applications.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.

[BibT_eX]

[DOI]

Marco Domenico Santambrogio

Riccardo Cattaneo

Gianluca Durelli

Alessandro Antonio Nacci

Marco Domenico Santambrogio

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Runtime adaptation on dataflow HPC platforms.

[BibT_eX]

[DOI]

Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012

TaBit: A framework for task graph to bitstream generation.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Automatic run-time manager generation for reconfigurable MPSoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Antonio Miele

Proceedings of the 2012 International Symposium on System on Chip, 2012

On the automatic integration of hardware accelerators into FPGA-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An open-source design and validation platform for reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Ioannis Papaefstathiou

Oliver Pell

M. Robart

Dirk Stroobandt

Tim Todman

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

On the Development of a Runtime Reconfigurable Multicore System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Catalin Bogdan Ciobanu

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011

A design methodology for the automatic sizing of standard-cell libraries.

[BibT_eX]

[DOI]

Davide Pandini

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Combined architecture and hardening techniques exploration for reliable embedded system design.

[BibT_eX]

[DOI]

Cristiana Bolchini

Antonio Miele

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A design methodology to implement memory accesses in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Evaluating Static CMOS Complex Cells in Technology Mapping.

[BibT_eX]

[DOI]

Davide Pandini

Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

A runtime adaptive controller for supporting hardware components with variable latency.

[BibT_eX]

[DOI]

Vito Giovanni Castellana

Silvia Lovergine

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

Design methodologies for improving embedded systems with hardware accelerators.

[BibT_eX]

[DOI]

PhD thesis, 2010

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

IEEE Micro, 2010

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells.

[BibT_eX]

[DOI]