Christian Piguet

Marc Pons

Daniel Séverac

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Highly energy-efficient and quality-tunable inexact FFT accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

Designing Energy-Efficient Arithmetic Operators Using Inexact Computing.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation.

[BibT_eX]

[DOI]

Pierre-François Rüedi

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Electronics for a greener planet.

[BibT_eX]

[DOI]

Gabriel Marchesan Almeida

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Why design reliable chips when faulty ones are even better.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2013, 2013

Improving energy gains of inexact DSP hardware through reciprocative error compensation.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.

[BibT_eX]

[DOI]

Fabrice Lemonnier

Philippe Millet

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Event-driven asynchronous voltage monitoring in energy harvesting platforms.

[BibT_eX]

[DOI]

Jean-Frédéric Christmann

Edith Beigné

Cyril Condemine

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Maximum delay variation temperature-aware standard cell design.

[BibT_eX]

[DOI]

Marc Pons

Jean-Luc Nagel

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Fixed origin corner square inspection layout regularity metric.

[BibT_eX]

[DOI]

Marc Pons

Marc-Nicolas Morgan

Kirthi Krishna Muntimadugu

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Energy harvesting and power management for autonomous sensor nodes.

[BibT_eX]

[DOI]

Jean-Frédéric Christmann

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling.

[BibT_eX]

[DOI]

Lingamneni Avinash

Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011

Guest Editorial Special Issue on ISCAS 2010.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing.

[BibT_eX]

[DOI]

J. Low Power Electron., 2011

Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems.

[BibT_eX]

[DOI]

Jean-Frédéric Christmann

IEEE Des. Test Comput., 2011

Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Energy parsimonious circuit design through probabilistic pruning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Energy autonomous sensor systems: Towards a ubiquitous sensor technology.

[BibT_eX]

[DOI]

Microelectron. J., 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

Low-Power Heterogeneous Systems-on-Chips.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2008, 2008

2007

Chronique : Consommation statique. Modèles, évolutions et perspectives.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2007

Low Power Design in Deep Submicron 65 & 45 nm Technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Static and Dynamic Power Reduction by Architecture Selection.

[BibT_eX]

[DOI]

Christian Schuster

Jean-Luc Nagel

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Architectural and technology influence on the optimal total power consumption.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Locally switched and limited source-body bias and other leakage reduction techniques for a low-power embedded SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.

[BibT_eX]

[DOI]

J. Low Power Electron., 2005

Low-power CMOS circuits - technology, logic design and CAD tools.

[BibT_eX]

CRC Press, ISBN: 978-0-8493-9537-6, 2005

2004

Guest Editorial.

[BibT_eX]

[DOI]

Narayanan Vijaykrishnan

IEEE Trans. Very Large Scale Integr. Syst., 2004

Power consumption reduction in systems on Chip (SoCs).

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2004

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Noise Margin in Low Power SRAM Cells.

[BibT_eX]

[DOI]

Stefan Cserveny

Jean-Marc Masgonty

Proceedings of the Integrated Circuit and System Design, 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Extremely Low-Power Logic.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Stand-by Power Reduction for Storage Circuits.

[BibT_eX]

[DOI]

S. Cservany

Jean-Marc Masgonty

Proceedings of the Integrated Circuit and System Design, 2003

2002

The First Quartz Electronic Watch.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001

Low-power low-voltage library cells and memories.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Low-power systems on chips (SOCs).

[BibT_eX]

[DOI]

Marc Renaudin

Thierry J.-F. Omnés

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Double-Latch Clocking Scheme for Low-Power I.P. Cores.

[BibT_eX]

[DOI]

Claude Arm

Jean-Marc Masgonty

Proceedings of the Integrated Circuit Design, 2000

1999

An On-Line Arithmetic Based FPGA for Low-Power Custom Computing.

[BibT_eX]

[DOI]

Arnaud Tisserand

Pierre Marchal

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998

Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Design of low-power libraries.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

Low-power design of 8-b embedded CoolRisc microcontroller cores.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

1996

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Functional Organisms Growing on Silicon.

[BibT_eX]

[DOI]

Pascal Nussbaum

Pierre Marchal

Proceedings of the Evolvable Systems: From Biology to Hardware, 1996

Speeding-up Digital Ecologies Evolution Using a Hardware Emulator: Preliminary Results.

[BibT_eX]

[DOI]

Proceedings of the Evolvable Systems: From Biology to Hardware, 1996

Low-Power Embedded Microprocessor Design.

[BibT_eX]

[DOI]

Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995

Logic design for low-voltage/low-power CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

A New Paradigm for Developing Digital Systems Based on a Multi-Cellular Organization.

[BibT_eX]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Embryonics: The Birth of Synthetic Life.

[BibT_eX]

[DOI]

Proceedings of the Towards Evolvable Hardware, 1995

1994

An 8-bit multitask micropower RISC core.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, August, 1994

Embryonics: Designing Programmable Circuits with Biological-like Properties.

[BibT_eX]

Proceedings of the 12st IASTED International Conference on Applied Informatics, 1994

1991

Multiprocess architecture for watch applications.

[BibT_eX]

[DOI]

J.-F. Perotto

A. Kägi

Microprocessing and Microprogramming, 1991

Design methodologies and CAD tools.

[BibT_eX]

[DOI]

Evert Dijkstra

Integr., 1991

1990

Binary-decision and RISC-like machines for semicustom design.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1990

One-chip low-power multiprocessor.

[BibT_eX]

[DOI]

J.-F. Perotto

C. Voirol

Microprocessing and Microprogramming, 1990

1988

On the use of modulo arithmetic comb filters in sigma delta modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1988

1987

A design methodology of microprogrammed controllers for custom CMOS IC's.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1987

1986

On minimizing memory in systolic arrays for the dynamic time warping algorithm.

[BibT_eX]

[DOI]

Evert Dijkstra

Integr., 1986

A new systolic decomposition for the dynamic time warping algorithm.

[BibT_eX]

[DOI]

Evert Dijkstra

Proceedings of the IEEE International Conference on Acoustics, 1986

1983

Design methodology for full custom CMOS microcomputers.

[BibT_eX]

[DOI]