Christian Pacha

According to our database¹, Christian Pacha authored at least 24 papers between 1997 and 2016.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2016

Thermal issues in test: An overview of the significant aspects and industrial practice.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2009

Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.

[BibT_eX]

[DOI]

Thomas Baumann

Doris Schmitt-Landsiedel

Christian Pacha

Proceedings of the 46th Design Automation Conference, 2009

2007

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

IEEE J. Solid State Circuits, 2007

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.

[BibT_eX]

[DOI]

Gustavo Neuberger

Fernanda Gusmão de Lima Kastensmidt

Proceedings of the IFIP VLSI-SoC 2007, 2007

A merged MuGFET and planar SOI process.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

Advances in Multi-Gate MOSFET Circuit Design.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

Gerhard Knoblinger

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

Christian Pacha

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

IEEE J. Solid State Circuits, 2006

Circuit design issues in multi-gate FET CMOS technologies.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.

[BibT_eX]

[DOI]

Doris Schmitt-Landsiedel

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2003

Circuit and application aspects of tunnelling devices in a MOBILE configuration.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2003

2002

Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE).

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Experimental threshold logic implementations based on resonant tunnelling diodes.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Tunnelling Diode Technology.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

Threshold logic circuit design of parallel adders using resonant tunneling devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Manufacturability and robust design of nanoelectronic logic circuits based on resonant tunnelling diodes.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2000

Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

Resonant Tunneling Transistors for Threshold Logic Circuit Applications.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Parameter Determination for Nano-Scale Modelling.

[BibT_eX]

[DOI]

Marc Thomas

Christian Pacha

Karl Goser

Proceedings of the Computational Intelligence, 1999

1997

Aspects of systems and circuits for nanoelectronics.

[BibT_eX]

[DOI]

Proc. IEEE, 1997

Christian Pacha

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