Christian Mayr
Orcid: 0000-0003-3502-0872Affiliations:
- Dresden University of Technology, Institute of Circuits and Systems, Germany
According to our database1,
Christian Mayr
authored at least 122 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
J. Syst. Archit., 2024
SpiNNaker2: A Large-Scale Neuromorphic System for Event-Based and Asynchronous Machine Learning.
CoRR, 2024
Designing a Power and Speed Adaptive 60 GHz Receiver in 22 nm FD-SOI CMOS for Tactile Internet Applications.
IEEE Access, 2024
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Scalable Event-by-Event Processing of Neuromorphic Sensory Signals with Deep State-Space Models.
Proceedings of the International Conference on Neuromorphic Systems, 2024
Proceedings of the International Conference on Neuromorphic Systems, 2024
Fast Switching Serial and Parallel Paradigms of SNN Inference on Multi-Core Heterogeneous Neuromorphic Platform SpiNNaker2.
Proceedings of the International Conference on Neuromorphic Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
CoRR, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
Proceedings of the IEEE Conference on Network Function Virtualization and Software Defined Networks, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.
Proceedings of the 20th International SoC Design Conference, 2023
Efficient recurrent architectures through activity sparsity and sparse back-propagation through time.
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the 8th International Conference on Frontiers of Signal Processing, 2023
Performance models and energy-optimal scheduling of DNNs on many-core hardware with dynamic power management.
Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI, 2023
Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI, 2023
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Efficient Algorithms for Accelerating Spiking Neural Networks on MAC Array of SpiNNaker 2.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Computers, 2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022
Int. J. Neural Syst., 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the Workshop on Artificial Intelligence Safety 2022 (AISafety 2022) co-located with the Thirty-First International Joint Conference on Artificial Intelligence and the Twenty-Fifth European Conference on Artificial Intelligence (IJCAI-ECAI-2022), 2022
Hardware-Efficient Ultrasonic Entrance Counting: Comparing Different Machine Learning Approaches.
Proceedings of the 26th International Conference on Pattern Recognition, 2022
Prototyping of Low-Cost Configurable Sparse Neural Processing Unit with Buffer and Mixed-Precision Reshapeable MAC Array.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022
Proceedings of the 7th International Conference on Frontiers of Signal Processing, 2022
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
Real-time Radar Gesture Classification with Spiking Neural Network on SpiNNaker 2 Prototype.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey.
IEEE Trans. Biomed. Circuits Syst., 2021
IEEE Open J. Circuits Syst., 2021
Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control.
Neuromorph. Comput. Eng., 2021
IEEE Des. Test, 2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021
Proceedings of the IEEE Radio and Wireless Symposium, 2021
Low Power CMOS Thyristor-Based Relaxation Oscillator with Efficient Current Compensation.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IECON 2021, 2021
Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 7th International Conference on Event-Based Control, 2021
Proceedings of the 22nd Engineering Applications of Neural Networks Conference, 2021
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
2020
Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.
J. Signal Process. Syst., 2020
Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi.
CoRR, 2020
A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020
Event-based Neural Network for ECG Classification with Delta Encoding and Early Stopping.
Proceedings of the 6th International Conference on Event-Based Control, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Biomed. Circuits Syst., 2019
SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.
CoRR, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Application-specific architectures for energy-efficient database query processing and optimization.
Microprocess. Microsystems, 2017
CoRR, 2017
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.
CoRR, 2017
CoRR, 2017
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
IEEE Trans. Biomed. Circuits Syst., 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Event-based softcore processor in a biohybrid setup applied to structural plasticity.
Proceedings of the International Conference on Event-based Control, 2015
2014
Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.
CoRR, 2014
CoRR, 2014
VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Proceedings of the Advances in Neural Information Processing Systems 25: 26th Annual Conference on Neural Information Processing Systems 2012. Proceedings of a meeting held December 3-6, 2012
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 18th European Symposium on Artificial Neural Networks, 2010
2009
Microelectron. J., 2009
Neurocomputing, 2009
On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz.
Comput. Intell. Neurosci., 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Untersuchungen zur Implementierung von Bildverarbeitungsalgorithmen mittels pulsgekoppelter neuronaler Netze.
PhD thesis, 2008
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
2007
IEEE Trans. Neural Networks, 2007
Nearest Neighborhood Grayscale Operator for Hardware-Efficient Microscale Texture Extraction.
EURASIP J. Adv. Signal Process., 2007
Proceedings of the 7th International Conference on Hybrid Intelligent Systems, 2007
2005