Christian Landrault
According to our database1,
Christian Landrault
authored at least 84 papers
between 1978 and 2009.
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Bibliography
2009
IET Comput. Digit. Tech., 2009
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.
J. Electron. Test., 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
2008
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 12th European Test Symposium, 2007
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
Proceedings of the 12th European Test Symposium, 2007
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
Proceedings of the Integrated Circuit and System Design, 2005
2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
J. Electron. Test., 2003
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
J. Electron. Test., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
2001
J. Electron. Test., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Random Adjacent Sequences: An Efficient Solution for Logic BIST.
Proceedings of the SOC Design Methodologies, 2001
Interconnect Capacitance Modelling in a VDSM CMOS Technology.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
J. Electron. Test., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 4th European Test Workshop, 1999
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts.
Proceedings of the 1999 Design, 1999
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Integr., 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
J. Electron. Test., 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors.
Proceedings of the Fifth International Conference on VLSI Design, 1992
Proceedings of the Fifth International Conference on VLSI Design, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
1990
Proceedings of the European Design Automation Conference, 1990
1980
IEEE Trans. Computers, 1980
1978
Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults.
IEEE Trans. Computers, 1978
SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems.
Proceedings of the Information Technology '78: Proceedings of the 3rd Jerusalem Conference on Information Technology (JCIT3), 1978