Christian Jacobi

Orcid: 0000-0003-0522-1630

Affiliations:
  • IBM Germany
  • Saarland University, Saarbrücken, Germany (PhD 2002)


According to our database1, Christian Jacobi authored at least 31 papers between 1999 and 2023.

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Bibliography

2023
Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability.
IEEE Micro, 2023

2022
AI accelerator on IBM telum processor: industrial product.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Real-time AI for Enterprise Workloads: the IBM Telum Processor.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020
History of IBM Z Mainframe Processors.
IEEE Micro, 2020

Design of the IBM z15 microprocessor.
IBM J. Res. Dev., 2020

Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019

2018
New database compression assists in the IBM z14 processor.
IBM J. Res. Dev., 2018

Performance innovations in the IBM z14 platform.
IBM J. Res. Dev., 2018

Design of the IBM z14 microprocessor.
IBM J. Res. Dev., 2018


2015
The IBM z13 multithreaded microprocessor.
IBM J. Res. Dev., 2015

2013
IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor.
IEEE Micro, 2013

2012
IBM zEnterprise 196 microprocessor and cache subsystem.
IBM J. Res. Dev., 2012

Transactional Memory Architecture and Implementation for IBM System Z.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2008
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
IBM POWER6 accelerators: VMX and DFU.
IBM J. Res. Dev., 2007

2006
Putting it all together - Formal verification of the VAMP.
Int. J. Softw. Tools Technol. Transf., 2006

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.
IEEE J. Solid State Circuits, 2006

Evaluating coverage of error detection logic for soft errors using formal methods.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Formal Verification of the VAMP Floating Point Unit.
Formal Methods Syst. Des., 2005

Automatic Formal Verification of Fused-Multiply-Add FPUs.
Proceedings of the 2005 Design, 2005

Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003
Cryptographically Sound and Machine-Assisted Verification of Security Protocols.
Proceedings of the STACS 2003, 20th Annual Symposium on Theoretical Aspects of Computer Science, Berlin, Germany, February 27, 2003

Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002
Formal verification of a fully IEEE compliant floating point unit.
PhD thesis, 2002

Deriving Cryptographically Sound Implementations Using Composition and Formally Verified Bisimulation.
Proceedings of the FME 2002: Formal Methods, 2002

Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2000
Proving the Correctness of a Complete Microprocessor.
Proceedings of the Informatik 2000, 2000

1999
Highly Concurrent Locking in Shared Memory Database Systems.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999


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